Electronic Design Automation

TSMC Certifies Mentor, Synopsys for 10nm FinFET Design

08 April 2015

EDA software vendors Mentor Graphics Corp. and Synopsys Inc. have announced certification of design software for Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC)'s 16-nanometer(nm) FinFET plus manufacturing process (16FF+) and its follow-on 10nm FinFET process.

The two companies join Cadence Design Systems Inc. (San Jose, Calif.), which made a similar announcement (see Cadence Tools Certified for TSMC's 10nm FinFET Process).

Mentor (Wilsonville, Oregon) says its Calibre physical verification and design for manufacturing platform and its Analog FastSpice circuit verification platform have been certified by TSMC based on the current version of the 10nm manufacturing process design rules and Spice models. The Olympus-SoC digital design platform is in the process of receiving TSMC validation. Mentor has also completed 16FF+ process version 1.0 certification across the Calibre, Olympus-SoC and AFS platforms.

At the same time, Synopsys (Mountain View, Calif.) announced that TSMC has concluded 16FF+ v1.0 certification on a comprehensive set of its custom and digital design tools. This certification enables mutual customers to deploy tools in Synopsys' Galaxy Design Platform for 16nm production designs and early 10nm engagements.

"Mentor's design solutions have successfully meet the accuracy and compatibility requirements for TSMC 10nm FinFET technology, so customers can initiate their designs with accurate verification solutions," says Suk Lee, TSMC senior director of design infrastructure marketing division, in a statement issued by Mentor.

Questions or comments on this story? Contact peter.clarke@globalspec.com

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