Electronic Design Automation

Cadence Looks to Improve Position in Digital Design Tools

10 March 2015

In an effort to boost its market share in the digital design tool space, EDA vendor Cadence Design Systems Inc. launched a new physical implementation platform at its CDNLive users' conference.

Cadence has long had the dominant analog design tool set in the EDA landscape. On the digital side, however, Cadence has lagged its larger rival, Synopsys Inc. The new physical implementation platform, dubbed Innovus, is Cadence's attempt to bridge that gap.

"Cadence has always been known as an analog company," said Anirudh Devgan, senior vice president of the Digital and Signoff group at Cadence. "The question on everyone's mind is, 'Can Cadence be best-in-class in digital?'"

Innovus' concurrent clock and datapath optimization, and clock-tree debugger.Innovus' concurrent clock and datapath optimization, and clock-tree debugger. Cadence (San Jose, Calif.) claims Innovus—built from the ground up over a period of several years—provides a 10 to 20 percent improvement in design power, performance and area (PPA) and up to a 10-fold reduction in turnaround time of advanced designs at the 16nm node and below.

Cadence President and CEO Lip-Bu Tan has recently been touting Cadence's advancements in digital design tool technology and market share. During the company's fourth quarter earnings call last month, Tan said Cadence had more than 10 "full flow" digital design wins in 2014. The company derived 28 percent of its revenue in the fourth quarter from digital IC and signoff products.

While Cadence's Encounter physical implementation system has roughly 40 percent market share, according to Devgan, it has for years trailed Synopsys' IC Compiler product—especially among top 10 semiconductor vendors.

"We have very good market share, but we want to have much better share among the top 10," Devgan said. “That's where they are spending a lot of money."

Anirdu DevganAnirdu DevganDevgan, who calls the Innovus launch the most significant for Cadence in the past five to 10 years, said the tool was built-in house by a team of engineers that has been augmented by between 90 and 100 people in recent months.

"Over the past two years, we have hired a lot of very smart people," Devgan said. "This [launch of Innovus] is the result of that."

Innovus is already in use at several customer locations. Cadence's announcement of the product included endorsements from ARM, Freescale, Juniper Networks, Renesas and MaxLinear.

Cadence touted several capabilities of the Innovus tool, including:

  • A new GigaPlace solver-based placement technology that is slack-driven and topology-, pin-, access- and color-aware, enabling optimal pipeline placement.
  • Advanced timing- and power-driven optimization that is multi-threaded and layer aware.
  • Concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability.
  • Slack-driven routing with track-aware timing optimization that tackles signal integrity early on.

Innovus also offers capabilities that boost turnaround time for each place-and-route iteration, Cadence said. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs, according to the company.

Related links:


IHS Semiconductors & Components

News articles:

Powered by CR4, the Engineering Community

Discussion – 0 comments

By posting a comment you confirm that you have read and accept our Posting Rules and Terms of Use.
Engineering Newsletter Signup
Get the GlobalSpec
Stay up to date on:
Features the top stories, latest news, charts, insights and more on the end-to-end electronics value chain.
Weekly Newsletter
Get news, research, and analysis
on the Electronics industry in your
inbox every week - for FREE
Sign up for our FREE eNewsletter