Foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is aiming for "risk production" of integrated circuits on a 7nm manufacturing process in 2017.
On April 16, while providing a technical update to financial analysts, Mark Liu, co-CEO of TSMC, said that the 7nm development program had begun in 2014 and collaboration activity had begun with several major customers. "The 7-nanometer technology risk production date is targeted at early 2017," says Liu.
Risk production is where TSMC's clients are running complete circuits, rather than test structures, but potentially still making changes to the process and/or the design to optimize performance and get yield up to commercially acceptable levels. Because the process is not finalized, such production is not guaranteed by TSMC and is at the customers' own risk.
The risk production phase can take about six months. For example, TSMC announced in November 2014 that its 16FF+ process was in risk production and that it anticipated volume production would begin in July 2015.
Therefore, with 7nm risk production starting early in 2017, there is an expectation that volume production could begin in the fourth quarter of 2017 and contribute to TSMC revenues in 2018.
Liu also updated analysts on the status of TSMC's next generation process technology—10nm FinFET—saying that the process would be qualified for design work in the fourth quarter of 2015 with volume production ramp expected to start in the fourth quarter of 2016. The process is expected to contribute to revenues in early 2017, Liu says.
"We have successfully achieved fully functional yields of our 256Mbit SRAM [test vehicle],” Liu says. “Currently, we have more than 10 customers fully engaged with us on 10nm. We still expect to have 10nm volume ramp in fourth quarter 2016 and to contribute billing in early 2017.”
Two-year Then One-year Intervals
This would put the 7nm process approximately one year behind the 10nm FinFET process, which would have lagged 16FF+ by two years.
This quicker migration to 7nm may be difficult, as there are still uncertainties about transistor construction at this geometry. Different research groups have looked at several different material regimes for the active channel in 7nm FinFET transistors. These include III-V compound semiconductor, germanium, carbon and molybdenum disulphide layers put down on a silicon wafer. It is possible that a 7nm process will include multiple types of transistor for n- and p-type logic transistors and for the formation of memory.
One of the largest uncertainties is the lithography to be used at 7nm. Extreme ultraviolet (EUV) lithography is seen as necessary and potentially available for the 7nm node (see Intel Orders 15 EUV Lithography Systems).
The 10nm process already appears destined to start using multipatterning of 193nm wavelength immersion lithography. It may be technically possible, but the multipatterning will make it expensive, as circuits have to be exposed multiple times to define a single pattern in photoresist for subsequent etching.
Liu provided an update on progress with EUV, saying that TSMC's two development tools—NXE3300 machines from ASML—have been upgraded with 80W light sources and are achieving average throughputs of a few hundred wafers per day.
"Although today the process on record of both 10-nanometers and 7-nanometer are on immersion tools with innovative multiplepatterning techniques, we will continue to look for opportunity to further reduce the wafer cost and simplify the process flow by inserting EUV layer in the process," says Liu.
Liu explained that using EUV would simplify production by removing multiple layers, which in turn helps with yield improvement, providing a double benefit. But where and when EUV can be inserted into production depends on EUV tools meeting a minimum threshold of productivity.
Although TSMC has seen one-day performance of up to 1,000, the average is still a few hundreds, Liu says. "And we need to get to more than 1,000 [wafers per day] to consider a schedule to put it into the production," Liu says.
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