Synopsys Inc. and Samsung Foundry have announced their latest collaboration on advanced manufacturing process technology nodes.
Announced at the Samsung Advanced Foundry Ecosystem (SAFE) Forum 2026, this latest collaboration includes a portfolio of production-ready, AI-powered electronic design automation (EDA) tools, certified interface IP and silicon-based test capabilities.
Synopsys said these new tools will allow Samsung Foundry users to bring differentiated AI and multi-die designs to market faster and improved quality.
“Close alignment across design, test, and manufacturing are critical to the success of AI and multi-die designs on advanced nodes,” said Hyung-Ock Kim, VP and head of the Foundry Design Technology Team at Samsung Electronics. “Our continued close collaboration with Synopsys delivers silicon-based, customer-validated solutions that help our customers reduce design integration risk, improve silicon predictability, and move confidently from design to production for their most innovative solutions.”
Details of the collaboration
The production-ready flows and improved PPA on third generation 2 nm class process will allow users to migrate to advanced Samsung Foundry nodes. The Synopsys Fusion Compiler on third-generation 2 nm class process has improved power and performance compared to second-generation 2 nm class process.
The Synopsys PrimeShield Process Sensitivity Analysis and PVT Explorer support design specific optimization and engineering change order decisions during signoff.
The AI-powered test tools help reduce test patterns and test cycles by up to 20% while preserving fault coverage on system-on-chip and multi-die designs manufactured by Samsung Foundry.
Meanwhile, the companies are enabling scalable 3D multi-die designs through certified multi-physics signoff solutions through Synopsys’ 3DIC Compiler.
Finally, the expanded IP portfolio includes:
- Embedded memories
- Logic libraries
- GPIOs
- Security IP
- SLM
