Heterogeneous integration of semiconductor sub-components in a single package is not a new design approach, nor are some of the advanced packaging approaches used in commercial products. Heterogeneous integration has allowed a huge range of new products to reach the market with greater reliability and yield compared to monolithic components. Examples where advanced packaging has made major inroads include mobile devices, server architecture, advanced networking processors and high density/high compute processors like FPGAs.
The chiplets in a package can’t exist in a vacuum, they need to communicate with each other to exchange data and enable meaningful experiences for end users. Semiconductor vendors have been developing their own interface standards for their chiplets in heterogeneously integrated components, but there are also vendor agnostic options for chiplet interfaces. The EDA software market is also catching up to chiplet design requirements with specialized tools and access to PHY IP.
Chiplets rely on vendor standards and open standards
The transition to chiplet-based semiconductor design was motivated by the demand for more cost-effective, more reliable packaging and lower-risk semiconductor manufacturing. Monolithic components can only pack more features into a package by increasing the size of the semiconductor die, which increases cost per chip produced. The other problem is the yield per chip can decrease, and that cost must be passed onto customers through higher component pricing.
With chiplets, you can reduce the costs and increase yield for the final product, but only if each chiplet has a method to communicate with other chiplets, as well as with other components via the system’s circuit board. With the IC substrate market growing and more packaging manufacturing capacity becoming available, more designs will be leveraging interface PHY IP to enable inter-chiplet communication inside the package.
Semiconductor vendors and the industry at large have responded with two groups of solutions: proprietary interface IP and vendor-agnostic interface standards.
Open standards
At present, the chiplet world only exists within a vendor’s own ecosystem, and the lack of standardization has prohibited the growth of a vendor agnostic chiplet ecosystem. There are three open standards available for chiplet-to-chiplet data transfer that attempt to resolve this problem. These are:
- Universal Chiplet Interface Express (UCIe)
- Data rates supported include 4 GT/s, 8 GT/s, 12 GT/s, 16 GT/s, 24 GT/s and 32 GT/s per lane
- Access the specification
- Bunch of wires (BOW)
- Data rates supported include 32 Gbps, 64 Gbps, 128 Gbps, 256 Gbps, 384 Gbps and 512 Gbps
- Access the specification
- High bandwidth memory (HBM)
- Data rate up to 6.4 Gbps over 16 independent channels in HBM3, equivalent to 819 GB/s per device
- Access the specification
Among these three standards, UCIe is receiving the most attention among the big players in semiconductor design and manufacturing. For semiconductor chiplet vendors, this particular standard is enabling new products that allow diverse compute options to be included in a single package. For example, it was announced in 2023 that QuickLogic would be developing FPGA chiplets with UCIe for connecting to other functional blocks in a package.
HBM is another game changer enabling 2.5D and 3D packaging with extremely high data transfer rates between CPU cores and peripheral memory blocks in-package. The high data transfer rates within a package will be the key to greater enablement of technologies like AI, which require very fast exchange of data between memory and processor cores. This also makes HBM very popular among these three open standards options.
Vendor standards may lack support
Semiconductor vendors have developed their own interface standards which are being used in their own products. This was only natural early on in chiplet development because the semiconductor manufacturers did not have the need or incentive to work with other vendors, and the lack of vendor agnostic standards required close collaboration between two companies. The biggest vendors will still have their proprietary standards, but these will not help grow the chiplet ecosystem or preclude the use of the open standards listed above. It is also doubtful that EDI tools will support full implementation of these standards in chip and package designs.
Getting back to the PCB
Chiplet-to-chiplet standards are great, but eventually a chip will have to communicate with other components in a PCB. The use of these standards only arises in-package; other standard interfaces are being implemented to reach into the PCB and allow communication with other components in an electronics assembly.
For example, most advanced components where a chiplet-based approach is implemented will include multiple high-speed interfaces for accessing peripherals. The most common examples include USB, a recent version of DDR (Gen 4 or Gen 5), a recent version of PCIe, networking or SerDes links, and memory interfaces like SATA.
EDA vendors are creating software and offering IP that enables implementation of these interfaces into chiplet blocks for a new component. The vendor support is expected to increase, which will enable further push of the chiplet ecosystem to an array of specialized low-volume application areas. Combined with greater packaging and substrate fabrication capacity, a robust chiplet market can eventually emerge that will bring access to custom chip designs to many more small players in the electronics industry.
