MEMS and Sensors

Two big reliability problems in advanced packaging

09 May 2024
Worldwide advanced packaging capacity is projected to rise until 2030 with chiplet based designs rising fast. But two reliability challenges are also rising regarding electromigration and thermos-mechanical stress between dies in the assembly. Source: Grispb/Adobe Stock

Even with advanced packaging, what’s old eventually becomes new again, and leads to reliability challenges in packaging assemblies and substrates. Chips have been packing more compute into smaller spaces ever since people have been writing about chips (and packaging). The result in on-die interconnects and in substrates has been an increase in current density, which creates challenges in terms of heat and electromigration.

Techniques to handle heat were much easier in chips built from monolithic dies. Today, newer advanced components have embraced heterogeneous integration and are being built from chiplets. Concerns relating to electromigration and thermo-mechanical stresses are two of the major reliability factors the packaging industry needs to overcome. There is potentially a path forward that can be accomplished in EDA software, but this requires collaboration with OSATs and creation of assembly development kits (ADKs), which are still in their infancy and require more research to achieve effectiveness.

Chiplet-based package reliability concerns

The two big reliability concerns in chiplet based packaging are electromigration and thermo-mechanical stress between dies in the assembly. Electromigration is not new and its occurrence in conductors is well-understood. In advanced packaging with chiplets, the smaller interconnect sizes in chiplets and the substrate creates higher current densities, which is know to increase electromigration.

The other big reliability concern is thermo-mechanical stress, which is an important reliability concern due to the various materials in the chiplet stack. Thermo-mechanical stress arises throughout a package as it heats up and reaches an equilibrium temperature; the many material interfaces and mismatches in material properties lead to stress concentrations throughout the package. A related problem is mismatches in thermal conductivity values, which create an unpredictable equilibrium temperature distribution, and this will affect the resulting stress distribution at equilibrium.

Thermo-mechanical reliability

The three thermal parameters that are critical in chip and packaging materials are the material thermal conductivity, coefficient of thermal expansion (CTE), and glass transition temperature (Tg). These three material properties each determine how the components in a package experience heat-induced stress during operation, as well as the during assembly processes.

During package assembly, the processing goal is completely uniform heating of the structure in reflow and bonding as this will help prevent cracking of silicon structures or conductors. Uniform heating of the components ensures they all come to a thermal equilibrium without temperature offsets, which then minimizes heat-induced stress on each component in the package assembly. In practice, this requires monitoring the package components while slowly drawing them up to the required temperature.

While cracking is possible in practice when assembly processing is not maintained properly, the more important aspect is maintaining dimensional stability across the entire package. Conductor and stacking features in 2.5D and 3D packages are extremely small, and the thermo-mechanical stress experienced during assembly creates appreciable deformation at material interfaces in the packaging. The result can be poor bonding between bumps, TSVs, and fanout routing which would create a risk of failure.

During operation, the potential for thermal-induced failure arises for the same reasons as seen in standard printed circuit boards and HDI circuit boards:

  • Repeated thermal cycling between extreme temperatures
  • Large CTE mismatches at material interfaces
  • One material exceeding its Tg value and creating excessive stress

Electromigration failure

The number of traces in a package/substrate required to connect 10 chiplets together could be in the 10's of thousands. When packing those interconnects into a small space, there will be much higher current density in conductors, to the point that electromigration becomes more likely during operation. In some packaging, the current density may reach close to maximum current density limits per design rules.

Electromigration is described by the well-known black equation, which hints at a thermal runaway effect from. The mean time to failure (MTTF) for an interconnect given its current density is:

The most common occurrence of electromigration in packaging or substrates is in the inter-chiplet interconnect, either in 2D or 3D. This generates heat that increases electromigration (reduces MTTF), resulting in further depletion of the conductor, which then produces more heat through resistive heating. Right at the interface between the trace and chiplet is a solder bump; this is a potential site for electromigration accumulation and thus failure of the attached conductor.

From PDK to ADK

The semiconductor industry, most notably foundries, are known to provide process development kits (PDKs) that specify design rules in a standard EDA file format. Once imported into a design environment, this eliminates much of the guesswork surrounding DFM. Advanced packaging requires something different: an assembly development kit (ADK), which specifies the assembly-driven design rules for a package designer.

Unfortunately for many design teams, there has not been enough collaboration between foundries, OSATs, and EDA vendors to promulgate ADKs. With the level of customization still required for chiplet layout and substrate/package design, there is still not a clear workflow for the development of ADKs. It is also unclear who is responsible for leading the way in ADK development. Should it be the EDA vendors, foundries, or OSATs? This is still an open question that can help the industry address the reliability challenges mentioned above.

To contact the author of this article, email GlobalSpecEditors@globalspec.com


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