Electronic design automation (EDA) heavyweight Cadence Design Systems Inc. has collaborated with United Microelectronics Corp. (UMC) to deliver a reference design toolset targeted at providing a silicon-ready 28nm ARM Cortex A7 MPCore-based system on chip (SoC).
The SoC is used in applications such as entry-level smartphones, tablets, high-end wearables and other advanced mobile devices. According to Cadence, using the tools from Cadence, UMC has reduced the time to tapout by 33 percent version its previous offerings and has achieved a performance of 1.7GHz. Cadence said the SoC achieved a dynamic power consumptions of less than 200mW – a 20 percent reduction over UMC’s previous flow.
Shih Chin Lin, senior division director of IP development and design support division at UMC, said in a statement the Cadence parallel architecture allowed UMC to “significantly reduce the time spent in signoff analysis, implementation and closure” to deliver a reference design that exceeded “our power, performance and area expectations.” Lin added UMC has tested the new chip to ensure it is a reliable 28nm silicon-ready reference design.
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