Startup Claims VISC Architecture Raises Processor Performance

03 November 2014

Soft Machines Inc. (Santa Clara, Calif.) – a startup founded in 2006 and which has raised more than $125 million in funding – has disclosed details of its virtual instruction set computing (VISC) architecture, which the company claims can provide 3 to 4 times the instruction per clock cycle (IPC) performance of rival architectures such as ARM and x86. This, in turn, can translate into a 2 to 4 times performance per watt advantage, the company states.

The VISC architecture has been developed in response to limit on achievable clock frequency for single cores and the power-scaling and programming challenges for multi-core deployments. The company description portrays the architecture as a flexible and dynamic version of multicore processing and because of this modularity and symmetry claims it will be scalable from Internet of Things type applications up through mobile application processors and on to servers.

The company should be taken seriously because it was co-founded by a couple of former Intel engineers. One is Mohammad Abdallah, who now serves the company as chief technology officer. Prior to forming Soft Machines he spent ten years at Intel Corp. where he held a series of positions, most recently as a senior architect in Intel’s Microprocessor Architecture Group. The other is Mahesh Lingareddy, who serves as CEO. Prior to founding Soft Machines Lingareddy worked as a design manager in Intel’s microprocessor product group.

Lingareddy has also overseen the growth of the company into a 250-person startup with operations in the U.S., India and Russia. The company intends to pursue a business model similar to that of ARM, allowing companies to license its VISC architecture and create their own implementations.

Soft Machines list of investors impressive and includes Samsung Ventures, Advanced Micro Devices, Globalfoundries, Russia (Russian Venture Company and Rusnano) Abu Dhabi (Mubadala) and Saudi Arabia (King Abdulaziz City For Science and Technology and Taqnia) and other strategic investors.

It is also notable that the company's board of directors includes Sanjay Jha, CEO of Globalfoundries, as chairman; and entrepreneur Gordon Campbell, who helped create the fabless chip company business model with the founding of Chips & Technologies Inc. in 1985.

VISC architecture showing how single-threaded code is parallelized into hardware threadlets. Source: Soft Machines.

The VISC architecture is based on the concept of "virtual cores" and "virtual hardware threads." These virtual hardware threads should really be thought of as hardware threadlets as they are created by a process of concurrency extraction that is done at run time. In this way the VISC architecture can dynamically allocate computing resources across virtual cores based on the individual applications needs.

VISC uses a “virtual software layer” that makes VISC architecture applicable to existing as well as new software ecosystems. The VISC architecture scales by changing the number of virtual cores and virtual threads. This approach provides a single architecture capable of addressing the needs of applications spanning from the Internet of Things (IoT), to mobile, and to data center markets.

In operation, a global front-end fetches a single instruction stream and divides it into threadlets and sends them to multiple physical cores, which schedule and execute the instructions. Extensive and repeated grouping and renaming of registers is done on a by-threadlet basis. While there is an overhead associated with this it is more than compensated for by the improvement in instruction per cycle (IPC) throughput, the company indicates.

Soft Machines uses its own instruction set internally but provides software that converts standard instructions to the VISC ISA. It reportedly can provide an ARM-to-VISC conversion layer and has a prototype x86-to-VISC converter.

The company has developed a dual virtual core system-on-chip prototype and the VISC architecture was presented at the Linley Processor Conference held in Santa Clara, October 22 and 23. The prototype system-chip platform allows 3D, video DRAM controller and HD video and has been used to run Linux OS, UEFI (Unified Extensible Firmware Interface) Bios, benchmarks running on Linux and Android 4.0 (Ice Cream Sandwich).

Benchmark results are shown in the table and figure below. The table shows the dual-core VISC prototyping performing at a higher IPC than a series of ARM and Intel processors, while the figure companies the dual-core VISC prototype against a Cortex-A15 core and achieving between about twice and seven times the IPC on a series of benchmarks.

VISC achieves highest IPC in SPEC 2006 single-thread benchmark using GCC 4.6 compiler. Source: Soft Machines.

VISC dual virtual core prototype compared against Cortex-A15 single core processor in terms of performance/MHz. Scale shows performance against Cortex-A15 normalized at 1.00. Source: Soft Machines.

This ability to outperform even high-end ARM and Intel cores is another reason to take Soft Machines seriously, although it is noticeable that nowhere in the presentation materials is the clock frequency referenced. This may suggest that due to silicon complexity or the use of an FPGA as prototyping platform the implementation is limited in terms of the clock frequency, and absolute performance, it can achieve.

"We founded Soft Machines with the mission of reviving microprocessor performance-per-watt scaling. We have done just that with the VISC architecture, marking the start of a new era of CPU designs," said Abdallah, in a statement. "CPU scaling was declared dead when the power wall forced CISC- and RISC-based designs into multi-core implementations that require unrealistically complex multi-threading of sequential applications. The VISC architecture solves this problem 'under the hood' by running virtual hardware threads on virtual cores that far exceed the efficiency of software multi-threading."

It now waits to be seen which company will be first to declare that the VISC approach to improving IPC does indeed work across meaningful workloads and scales as the company claims. Could that company be investor Advanced Micro Devices with its devices made by foundry and investor Globalfoundries?

Related links and articles:

IHS MCU and MPU research

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