Semiconductor Value Chain

Startup Seeks Funds to Realize 'Belt' Processor

16 December 2013

A startup chip company that has been working quietly for ten years has come out of stealth-mode through a series of public and internet-mediated lectures. The company wants to draw attention to its innovative processor architecture and to raise funds enable the company to implement it in silicon.

The company is Out-of-the-Box Computing and founder Ivan Godard, who serves as chief technology officer and acting CEO, has claimed that the so-called Mill architecture should be able to provide ten times the performance of out-of-order superscalar processors, at equivalent clock frequencies in the same manufacturing process. The claim goes further saying that DSP-like computational efficiency can be brought general-purpose processing with power consumption and silicon area benefits.

In his lectures Godard has said that out-of-order superscalar processors spend much of their time and power consumption working out what to do next, renaming registers, or moving data around, and relatively little actually fulfilling the requirements of the program.

However, a Mill processor is a long way from realization. Godard has said that given funds and good execution it would likely take one year to 18 months to implement a version of the architecture in an FPGA. It would then take another year to 18 months to produce a custom silicon version, which puts dedicated Mill silicon two to three years away.

The Mill architecture is claimed to be innovative, and streamlined and therefore much more efficient. It is primarily notable for not including a conventional register set but instead having a FIFO in which to store operands. This FIFO is called a "belt" – as in conveyor belt – as newly created results from functional units drop on to the belt at the front end and drop off the belt at the end. However, functional units can grab data from anywhere on the belt through a form of positional and temporal addressing.

Compiler expert Ivan Godard is the public face of the group of engineers at OOTBC. He has given lectures on various aspects of the Mill architecture through the second half of 2013. The team behind the Mill has its origins at Philips Semiconductors, and its spin-off TriMedia Technologies Inc. TriMedia produced a 160-bit (five by 32-bit) very long instruction word (VLIW) architecture for use in audio-visual applications, which achieved some success in the 1990s.

There are some similarities between TriMedia and Mill architectures. Both are wide issue machines and in the case of Mill one instruction can have up to 33 individual MIMD (multiple instruction multiple data) operations depending on the Mill family member involved. But unlike the TriMedia DSP, the Mill is intended for broadly general-purpose logic and as competitor to the multi-cored out-of-order superscalar and RISC processors, the x86 and ARM processors that currently dominate.

Interestingly depending on the implementation of the Mill architecture the processors will have 8, 16 or 32-bit deep belt FIFOs. Godard has made the point in his lectures that the Mill architecture is scalable and therefore allows multiple processor instantiations aimed at different computing loads and supported by different sizes of cache and lengths of belt. He has referred to a high-end dual-core Mill implantation called Gold and a low-end design called Tin. The company reckons the Gold dual-core can process a theoretical 79.3-Gips (giga instructions per second) running at 1.2-GHz while consuming 28 watts.

Such theoretical performance is only achievable by keeping all functional units busy and not running no-ops and this will depend on the compiler.

In talks and interviews Godard has made the point that the Mill architecture is a 64-bit architecture and does not intend to compete at the low-end against microcontrollers but reckons it could be good for control-intensive computing in applications such as artificial intelligence, say as the controller for autonomous vehicles.

OOTBC has prepared a large number of patents on its belt-type computing processor but now requires funding to pay patent attorneys and also to upgrade EDA software as it goes into the implementation stage.

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