EDA software and IP licensor Synopsys Inc. has announced an upgrade to its ARC family of configurable processor cores, which the company says ship in 1.3 billion chips per year ship.
According to Synopsys (Mountain View, Calif.), ARC is the world's second most pervasive embedded processor architecture, trailing only market leader ARM. Only about one quarter of ARM's 2.5 billion IP shipments per quarter are specifically for embedded applications.
The ARC processor IP lies within the Synopsys' DesignWare library. The 32-bit HS34 and HS36 cores are the first members in a family of higher performance cores based on the ARCv2 instruction set architecture. They are the highest performance ARC processor cores developed to date, delivering 1.9 DMIPS/MHz at speeds up to 2.2 GHz in typical 28nm silicon Synopsys said.
The both come in single, dual or quad-core configurations with the difference between the two cores being that the HS34 is cache-less, while the HS36 includes up to 1-Mbyte of instruction and data cache memory.
Synopsys is pitching the cores as embedded processors on SoCs for use in solid-state drives, automotive controllers, media players, digital TV, set-top boxes and home networking products.
According to Paul Garden, a product marketing manager at Synopsys, configurability and accessiblity remain key strengths of the ARC architecture. ARC gives customers the ability to customize and optimize the core more than competing third-party IP cores, including ARM, Garden said. "Customers are very interested in that," he added.
Configurability of processor resources was a key characteristic of the ARC processor IP when it was first introduced in the 1990s.
The HS series processors retain the ability to include custom instructions, which can provide a significant benefit in reducing power consumption and silicon area for embedded applications. The configurability also continues with designers able to tailor instances of the cores for the optimum trade-off of performance, power and area. There are also ports for the integration of hardware accelerators. Native ARM, Amba AXI and AHB standard interfaces are configurable for 32-bit or 64-bit transactions.
When implemented in typical 28nm processes, the HS cores consume as little as 0.025mW/MHz in an area as small as 0.15 square millimeters. The cores feature a high-speed 10-stage pipeline that supports out-of-order execution to minimize idle processor cycles.
Synopsys claims that the ARCv2-based cores provide an 18 percent improvement in code density compared to previous generation ARC cores, thereby reducing memory requirements, which is also a significant way to reduce power consumption.
Garden noted that performance and power consumption are primary areas of customer interest. "We are in what we call the power-performance paradox," Garden said. "Everyone wants more performance and lower power. We see this in the embedded space. That's ultimately what we designed this product family for. We designed what we feel is a very efficient and power saving architecture without giving up any performance."
The cores are available to license and have development tool support. The Metaware development kit includes compiler and an instruction set simulator for pre-hardware software development.