Imagination Technologies Group plc (Kings Langley, England) announced the the first in its "Warrior" generation of MIPS cores. The announcement of the MIPS P5600 core is likely to be the most significant announcement since Imagination acquired MIPS Technologies Inc. at the end of 2012.
The P5600 is a Warrior-P class 32-bit core for which Imagination is making claims about having a "silicon footprint up to 30 percent smaller than comparable CPU cores," and superior performance of a factor of 1.2 to 2 times when compared to unnamed ARM CPU cores.
The core, an implementation of the MIPS 5 instruction set architecture, is suitable for manufacturing in 28-nm CMOS where it should be able to target a range of performance, power and area footprints at maximum clock frequencies from 1-GHz to above 2-GHz, the company said.
Imagination makes no explicit mention of support for a "big-little" approach to power-efficient processing, something that has been pioneered by rival IP supplier ARM and which has been used by some customers.
Nonetheless, Imagination's ambition for the P5600 core is large. The company reckons the core can be used for application processor SoCs in mobile phones and tablet computers as well as consumer electronics products such as set-top boxes, digital televisions audio systems, and home and office networking equipment and microservers.
The core will be available for licensing before the end of 2013. First SoCs based on the P5600 could appear in 2014 from lead customers that have been working on the core with Imagination prior to this announcement.
The "up to 30 percent" smaller footprint claim includes the negative numbers implying that the P5600 could be larger than comparable CPU cores. The claim is based on information derived from Samsung's presentation of the Exynos 5 Octa made at the International Solid-State Circuits Conference in February 2013, Imagination said. The Samsung chip is based on the ARM, big-little architecture and uses a quartet of big Cortex-A15s and four little Cortex-A7 cores
The P5600 is the first implementation of the MIPS Series5 architecture that covers both 32- and 64-bits. Imagination intends to round out the "Warrior" family over the next 12 months.
Features of the P5600 include: a 128-bit single-instruction multiple data (SIMD) to support imaging, multimedia codecs and DSP; hardware virtualization; support for up to six cores per cluster with cache coherency; virtual addressing; and extended physical addressing that allows a 32-bit system to address up to 40-bits of physical memory.
Imagination claimed that the P5600 achieves a benchmarked performance of 5 CoreMarks/MHz and 3.5-dhrystone MIPS/MHz. This data is preliminary and is based on an RTL simulation of the P5600 core and knowledge of existing proAptiv core running the GCC 4.9.0 compiler. In addition Imagination is claiming the performance is 1.2 to 2 times that of ARM cores based on publicly available information. Imagination did not indicate, which ARM cores it is making comparison with.
Mark Throndson, director of processor technology marketing at Imagination, is due to present more technical detail of the MIPS P5600 CPU family at the Linley Tech Processor Conference in Santa Clara, Calif., later this week.
"This is about much more than the arrival of yet another CPU IP core," said Tony King-Smith, executive vice president of marketing at Imagination, in statement. "This is the start of something much bigger—the rollout of a comprehensive family of next-generation CPUs that will change the CPU IP landscape forever. As we continue to roll out MIPS Series5 products to address the applications spectrum from entry-level to the high-end, we will provide levels of performance, efficiency and functionality that surpass other offerings in the market."
Imagination said the MIPS Series-5 Warrior cores will come in three classes—M, I and P—that will be progressions from the microApiv, interAptiv and proAptiv families, respectively.
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