Startup company Wave Semiconductor Inc. (Sunnyvale, Calif.) is getting close to coming to market having been founded in 2009 to work on a form of asynchronous logic called null-convention logic (NCL).
A 28m CMOS test-chip codenamed Shelby has been manufactured and according to a twitter message from the company it was able to run at a performance equivalent to greater than 10GHz by varying the voltage. Wave has assembled a team of experienced semiconductor industry executives as it prepares to launch products low-power self-synchronizing logic products based on an algebra called Wave Threshold Logic (WTL), an implementation of NCL.
The company co-founders are Peter Foley, who serves as CEO, and Karl Fant, who serves as chief scientific officer. Other executives who have joined the company include Richard Terrill, vice president of marketing. who has previously served in management roles with Altera and XMOS. The company is backed by Tallwood Venture Capital and Southern Cross Venture Partners and prior to co-founding Wave Foley was an "executive in residence" at Tallwood.
Fant is a longstanding expert in asynchronous logic and the research pedigree of null-convention logic stretches back through Theseus Logic Inc. to Theseus Research Inc. founded by Fant in 1990.
Azure Reconfigurable Clockless Logic
Azure is more coarse-grained than an a conventional FPGA and is based on an array of general-purpose byte-oriented processing elements that each as instruction and data cache and that are configured at run time. The processing elements are organized in clusters and super-clusters and can be reconfigured in a few milliseconds, without loss of data or state elsewhere on the chip, according to information at the company website. The block diagram also shows a couple of 32-bit RISC processors on-chip but whether these are licensed in or an internal development is not made clear. Similarly the relationship between these and the reconfigurable processing fabric is not detailed.
Not only can Azure processing elements execute code, exchange data, and self-coordinate at speeds well in excess of 5GHz they can operate across a voltage range from 300mV to 2200mV with a Vdd nominal of 850mV, the company states on its website. This gives the technology the potential to go down to near-and sub-threshold voltage operation.
Wave compares an Azure chip in 28nm with a 28nm FPGA for a variety of benchmarks, such as FIR filter, TCAM, FFT and Viterbi codec although, Azure's clockless operation does impact that. When normalized to an equivalent function and functional performance Azure typically consumes 67 percent less power and occupies 75 percent less die area, the company claims. Azure can also provide higher performance because it has no clock to limit the functionality. This can result in a 75 percent faster TCAM and 2.5x faster Viterbi codec function, the company adds.
Because WTL is a clockless logic it removes the need for global clocks and numerous registers and flip-flops used to latch bit values in clocked logic, which is a simplification and power reduction in itself. WTL is based on a state-holding monotonic threshold gates and multiwire encoding. The resulting logic system unifies data, synchronization and control and eliminates glitching, according to a technical backgrounder. WTL can reduce static power by 90 to 95 percent and dynamic power by about 50 percent, the company claims.
One of the most recent companies to try bringing asynchronous logic to market was Handshake Solutions NV (Eindhoven, The Netherlands), a spin-off from Philips Research. Working with ARM Holdings plc (Cambridge, England) Handshake produced the ARM996HS 32-bit RISC processor in about 2006. However despite a power consumption thought to be about one-third of its clocked equivalent the asynchronous processor failed to gain commercial traction.
Achronix Semiconductor Corp. a vendor of FPGAs now made for it by Intel using 22nm FinFET manufacturing process technology, originally announced its architecture was based on an asynchronous core. This allowed its first 40nm parts to achieve high performance. However apart from the implicit mention in the company name, there is little discussion of the asynchronous nature of its parts.
Among the disadvantages of asynchronous logic are that its performance varies with temperature, and this can dictate generous design guard-banding to maintain a design's integrity over a full temperature specification. Also there can be difficulties interfacing between clocked and clockless domains and rigorous testing of asynchronous circuits has proved difficult for some companies.
Fant is the author of Logically Determined Design a key text on clockless logic and null-convention implementation.
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