Belgian research institute IMEC has made III-V compound semiconductor FinFET devices integrated epitaxially on top of 300-mm silicon wafers.
The development will allow the building of heterogeneous ICs that combine conventional CMOS circuits with compound semiconductor circuits to address radio frequency and optoelectronic applications, IMEC (Leuven, Belgium) said. The fin of the FinFET devices is approximately 50 nm wide, IMEC said.
IMEC's process selectively replaces silicon fins with indium gallium arsenide (InGaAs) and indium phosphide (InP) and accommodates the close to 8 percent atomic lattice mismatch between silicon and InGaAs. The technique is based on trapping crystal defects to prevent propagation into the active transistor area, the use of trench structures and epitaxial process innovations. The resulting III-V-on-silicon FinFET shows excellent performance, IMEC said.
"The replacement of the polysilicon gate by the high-k metal gate in 45-nm CMOS technology in 2007 represented a major inflection in new material integration for the transistor. The ability to combine scaled non-silicon and silicon devices might be the next dramatic transistor facelift, breaking almost 50 years of all-silicon reign over digital CMOS. This work represents an important enabling step towards this new paradigm," said Aaron Thean, director of logic R&D at IMEC, in a statement.
"To our knowledge, this is the world’s first functioning CMOS-compatible III-V FinFET device processed on 300-mm wafers," said An Steegen, senior vice president of core CMOS at IMEC, in the same statement.
This research has been conducted as part of IMEC's "Core CMOS" program. The research was performed in cooperation with key partners including Intel, Samsung, TSMC, Globalfoundries, Micron, SK Hynix, Toshiba, Panasonic, Sony, Qualcomm, Altera, Fujitsu, Nvidia and Xilinx, IMEC said.
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