Supply Chain Management

Synopsys Tool Claims Big Throughput Boost

24 March 2014

EDA and IP provider Synopsys Inc. Monday (March 24) announced a new place-and-route tool that the company claims offers a 10-fold increase in physical design throughput.

IC Compiler II, the successor to Synopsys' popular IC Compiler place-and-route tool, was built from the ground up on a multi-thread infrastructure, according to the company. The new tool introduces ultra-high-capacity design planning, a new clock-building technology and advanced global-analytical closure techniques, according to Synopsys (Mountain View, Calif.). It has already been used in designs that have been taped out by several customers, Synopsys said.

According to Sanjay Bali, director of marketing for Synopsys, the new tool is the result of an engineering effort that spanned four to five years. Bali said Synopsys realized that in order to address the growing complexity of IC design the company needed to start from scratch with the successor to its popular IC Compiler product.

"We wanted to offer something that was orders of magnitude better, not just an incremental improvement," Bali said. To do that, he said, the company had to embark on a "revolutionary track" that took significant time and effort. "But we felt that we had to do that if we wanted to offer something that is orders of magnitude better," he said.

Bali stressed that early input from customers has been very positive. Synopsys has been working with several customers—including Imagination Technologies, LSI, Renesas, Samsung and STMicroelectronics—on the tool, which won't begin shipping until the middle of this year. Though the tool is technically still in development, some of these customers were so intrigued by its capabilities that they used it for designs even though it was not completely ready, Bali said.

Synopsys will continue to enhance and support the original IC Compiler, Bali said, enabling customers to continue using it on designs until they choose to move to IC Complier II.

Synopsys said IC Compiler II's new multi-threaded infrastructure enables it to handle designs with more than 500 million instances. The tool uses industry standard input and output formats, as well as familiar interfaces and process technology files, Synopsys said. It also features an innovative design storage capability, the company said.

While IC Compiler II offers a 10-fold performance boost, it also consumers five times less memory than the original IC Compiler, according to Synopsys. It also features block-level functionality powered by a new global-analytical optimization engine, a new clock generator and unique algorithmic capabilities in post-route optimization, which Synopsys said together enable enhanced quality of results in area, timing and power.

"IC Compiler II represented the single biggest leap in productivity we have seen in many years," said Tatsuji Kagatani, manager of the design automation department for Renesas's system integration business division, in a statement circulated by Synopsys.

Kagatani said that on a Renesas design, IC Compiler II exhibited at least a seven-fold improvement in runtime and a three-fold memory improvement while delivering competitive quality of results. Kagatani said Renesas is working with Synopsys to deploy IC Compiler II into production use.

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