Supply Chain Management

Synopsys' de Geus: FinFET Transition Gaining Momentum

21 August 2014

The transition from planar transistor to FinFET chip manufacturing is picking up pace and driving EDA opportunities in both design tools and IP cores, according to Aart de Geus, chairman and co-CEO of EDA software and circuit IP vendor Synopsys.

The adoption of the FinFET is going to provide a further ten years of Moore's Law and ten years of work for Synopsys – and other EDA and IP companies – de Geus said in a conference call with analysts to discuss the company's third fiscal quarter results. The Synopys CEO also portrayed fully-depleted silicon on insulator (FDSOI) technology as something getting consideration as a node extender at 28nm but which is still waiting for the large-scale foundry manufacturing capacity.

Synopsys Inc. (Mountain View, Calif.) made a net income of $65.7 million on sales revenue of $521.8 million in its third fiscal quarter, which ended July 31, 2014. The revenue was up 8 percent from the $482.9 million revenue recorded for the third quarter of fiscal 2013 and the net profit was up from $52.3 million in the same quarter a year before.

"Synopsys delivered an excellent fiscal third quarter, solidifying the year's financial outlook," said Aart de Geus, chairman and co-CEO of Synopsys, in a statement. "We shipped game-changing new products that are generating intense customer interest and high-impact results, and have already started a multi-year upgrade cycle. We also achieved encouraging results through Coverity, the recent acquisition that expands our total addressable market into the software quality, test and security space."

CEO de Geus said that customer demand has been strong and with semiconductor customer results have been trending better over the last couple of quarters the outlook was improving. De Geus said the acquisition of Coverity Inc., a provider of software quality, testing, and security tools announced in February 2014, had gone well and was in keeping with the industry trend towards greater software significance.

Aart de Geus, chairman and CEO of Synopsys: Moore's Law is alive and well.

During the fiscal quarter Synopsys introduced a significant upgrade to its circuit design toolset, IC Compiler II, which de Geus claimed provides a 10x improvement in design productivity. De Geus said that Moore's Law is alive and well that the FinFET segment is growing extremely quickly as is the pace of progress to 16/14nm and 10nm nodes. "Synopsys is tracking 150 FinFET design and tape-outs worldwide," de Geus told analysts on a conference call to discuss the financial results.

When asked about how much of Synopsys' revenue was associated with the leading-edge nodes at 45nm and below, de Geus said about 50 percent although he stressed that IC Compiler II could also provide throughput and density benefits at 65nm and older nodes.

Synopsys forecast revenue for the fourth fiscal quarter of between $537 million and $547 million, which would result in annual fiscal revenue of between $2.055 billion and $2.065 billion.

Such a push on FinFET

When asked if the move to FinFET production was having a greater impact on tools or IP de Geus said it drove both. Foundries rely on EDA companies, such as Synopsys, to do two or three things, de Geus said. These tasks are; to develop and tune EDA tools to manufacturing processes, prepare libraries and memory compilers, provider higher level IP and confirm that design flows work.

"The fact there is such a push on to FinFET has brought a wave of work on Synopsys but that's not a negative, it's a positive, an opportunity to drive the state-of-the-art forward. "The FinFET wave…guarantees 10 years of Moore's Law and we are very involved in making that happen," said de Geus.

When asked what Synopsys was doing to address demand for FDSOI, de Geus said: "We have been very competent in FDSOI for quite a while and the majority of the chips that have used that technology were taped out with our tools." He added: "FDSOI brings some of the promise of lower power to the 28nm planar transistor. So, when do stop 28/20nm and jump to the next wave? And quite a number of companies are right now using 28nm to the best of their abilities until FinFETs become economically more mature and there has been the proposal to use FDSOI as a way to get even better results out of 28nm for a lower price [than FinFET]. ST has had excellent results with this. The question remains, will there be broad foundry capacity for that? If yes, I am sure some customers will use it."

Related links and articles:

News articles:

Synopsys Tool Claims Big Throughput Boost

FDSOI: Is Cadence, Not Samsung, the Tipping Point?

Synopsys to Buy Software Quality and Security Firm Coverity

Cadence Keeps Consolidating with Jasper Purchase

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