A collaboration between Taiwan Semiconductor Manufacturing Corp (TSMC)., Synopsys Inc. and Ansys is furthering multi-die system design and manufacturing.
The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology will run on TSMC processes, allowing designers to tackle the challenges of multi-die systems. The solutions will run on TSMC’s 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard.
"The inflection point of silicon designs moving towards multi-die systems poses new challenges in power, thermal integrity and reliability signoff," said John Lee, vice president and general manager at Ansys. "These complex challenges require an integrated approach and a strong ecosystem to provide comprehensive solutions. Through our collaboration with Synopsys and TSMC, designers can leverage the full strength of our leading multi-die solutions and decades of expertise to accelerate silicon success."
Unlike monolithic system-on-chips, multi-die systems enable:
- Early architecture exploration
- Rapid software development and system validation
- Efficient die and package co-design
- Secure die-to-die connectivity
- Enhanced manufacturing and reliability
As part of the collaboration with TSMC and Ansys, Synopsys’ 3DIC compiler is integrated with TSMC 3Dblox and TSMC 3Dfabric technologies for 3D system integration, advanced packaging and a complete exploration-to-signoff implementation.
Additionally, Synopsys’ signoff solutions can be certified with TSMC technologies and integrated with Ansys RedHawk SC electrothermal multi-physics technology.
The successful tape-out of the Synopsys Universal Chiplet Interconnect Express (UCIe) PHY IP on the TSMC N3E process. UCIe is poised to become the de facto standard for low latency and secure die-to-die connectivity.
