To carve a path from billion to trillion-transistors on artificial intelligence chip designs, pure-play foundry leader Taiwan Semiconductor Manufacturing Co. (TSMC) and electronic design automation (EDA) giant Synopsys Inc. are expanding their partnership to include advanced EDA and IP solutions in TSMC’s most advanced processes.
Synopsys, Ansys and TSMC are joining forces to address multi-die design challenges with comprehensive system analysis flow. The most recent flow is based on Synopsys’ 3DIC Compiler unified exploration-to-signoff platform. This integrates 3DSO.ai and Ansys’ RedHawk-SC power integrity signoff platform for digital and 3D ICs.
"Synopsys' certified Custom Compiler and PrimeSim solutions provide the performance and productivity gains that enable our designers to meet the silicon demands of high-performance analog design on the TSMC N2 process," said Ching San Wu, Corporate VP at MediaTek. "Expanding our collaboration with Synopsys makes it possible for us to leverage the full potential of their AI-driven flow to accelerate our design migration and optimization efforts, improving the process required for delivering our industry-leading SoCs to multiple verticals."
More support
Synopsys is also collaborating with TSMC on backside routing capabilities for its A16 process in the digital design flow to address power distribution and signal routing.
Additionally, the companies are enabling tools on the cloud through TSMC’s Cloud Certification with EDA tools to deliver results and integrate TSMC’s advanced process technology. These tools include:
- Synthesis
- Place and route
- Static timing and power analysis
- Transistor-level static timing analysis
- Custom implementation
- Circuit simulation
- EMIR analysis
- Design rule checking