Samsung Electronics Co. Ltd. is looking to shore up its standing as world’s second biggest chipmaker by spinning off its foundry business in an effort to challenge the likes of pure-play foundry makers.
The company has unveiled a new foundry road map including process nodes in 8 nanometer, 7 nanometer, 6 nanometer, 5 nanometer, 4 nanometer and 18 nanometer fully depleted silicon on insulator (FD-SOI). Samsung says its foundry business will develop chips for hyperscale data centers, devices for the Internet of Things (IoT) and a host of smart, always-on connected devices.
Samsung’s 8 nanometer low power plus (8LPP) process will provide competitive scaling and provides boosts to performance and gate density compared to 10LPP. Meanwhile, its 7LPP will be the first semiconductor process to use an extreme ultra violet (EUV) lithography solution, Samsung says.
The 6LPP process will use Samsung’s smart scaling technology, which will be incorporated on top of the EUV-based 7LPP technology. The 5LPP extends the scaling limit of fin field effect transistor (FinFET) structure by implementing technology from the next process generation, 4LPP. That 4nm low power plus process will be using Samsung’s Multi Bridge Channel Field Effect Transistor (MMCFET) next generation architecture — a gate all around field effect transistor (GAAFET) technology that uses a nanosheet device to overcome physical scaling and performance limitations of FinFET.
Finally, Samsung’s FD-SOI process will be used for IoT applications, with Samsung planning to expand its 28FDS technology into a larger platform by incorporating radio frequency and eMRAM options.