At its annual Samsung Foundry Forum held this week, Samsung Electronics Co. Ltd. gave details regarding its next-generation 3 nm gate-all-around (GAA) manufacturing process.
The manufacturing technology is designed to provide up to a 45% reduction in chip area with 50% lower power consumption compared to Samsung’s 7 nm technology. Samsung said the process technology will be used in next-generation applications such as mobile, networking, automotive, artificial intelligence and the internet of things (IoT).
The details of its next-generation manufacturing technology comes just a few weeks after Samsung said it will invest $115 billion in non-memory related semiconductors for its foundry business. The plan is to take advantage of what analysts believe is a slow foundry market and the potential for Samsung to gain market share from leading foundry Taiwan Semiconductor Manufacturing Corp (TSMC).
The current Samsung foundry roadmap includes four fin field-effect transistor (FinFET)-based processes, from 7 nm down to 4 nm, that use extreme ultraviolet (EUV) technology as well as 3 nm GAA. In the second half of this year, Samsung is slated to start mass production of 6 nm process devices and complete its development of 4 nm processes. In the first half of 2020, the 5 nm FinFET process is expected to begin mass production.
Conventional GAA is based on nanowire and requires a large number of stacks due to its channel width. Samsung’s GAA multi-bridge channel FET (MBCFET) uses a nanosheet architecture that enables a greater current per stack, the company said.
FinFET structures module the number of fins in a discrete way while the MBCFET providers design flexibility by controlling the nanosheet width, the company said. MBCFET is compatible with FinFET, allowing the two to share the same manufacturing technology and equipment, accelerating process development and production ramp-up.
