Power Semiconductors

Samsung Unveils Process Technology Roadmap Down to 3nm

23 May 2018

As one of the largest semiconductor manufacturers in the world, Samsung Electronics Co. Ltd. must keep up with the latest silicon innovations to stay ahead in the market.

In order to do this, Samsung Foundry has unveiled its process technology roadmap with new nodes down to 3 nanometers.

Samsung’s process technology roadmap begins at the 7 nm Low Power Plus (7LPP), which the company says is the first technology to use an EUV lithography solution and is ready for production in the second half of this year. Key intellectual properties (IP) are under development with a goal of completion to be in the first half of 2019.

Next on the roadmap is the 5 nm Low Power Early (5LPE) that will allow greater area scaling and ultra-low power benefits, followed by 4 nm Low Power Early/Plus (4LPE/LPP) that will extend Samsung’s highly mature and verified FinFET technology. With a smaller cell size, improved performance and faster ramp-up to the stable level of yield by adopting 5LPE migration, 4LPE/LPP will be the last generation of FinFET.

Finally, the 3 nm Gate-All-Around Early/Plus (3GAAE/GAAP) is the next-generation device architecture that is touted as overcoming the physical scaling and performance limitations of the FinFET architecture. Samsung said it is developing its GAA technology, Multi-Bridge Channel FET that uses a nano-sheet device. By enhancing the gate control, the performance of 3 nm nodes will be significantly improved, the company said.

To contact the author of this article, email PBrown@globalspec.com

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