Cortus SAS, developer of a proprietary 32bit RISC architecture that has mainly been deployed in deeply embedded applications, has announced the first implementation of its v2 instruction set, the APS23.
Cortus (Montpellier, France) is known for cores that are implemented in very few gates. It's first 32-bit core, the APS32 required only 7,000 gates and consumed 18-microwatts per megahertz. Cortus cores have been used in high-volume applications including automotive, imaging, M2M controllers, secure execution, sensors, SIM cards, PayTV cards and smart metering. Cortus IP has shipped in more than 700 million devices since the company was founded in 2005.
The second-generation instruction set is aimed at reducing the size of instruction memory and thereby further reducing system power consumption. The APS23 is an enhanced version of the APS3R and is aimed at low power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart.
In other words this is a revamp for Internet of Things type applications.
The APS23 core connected to peripherals. Source: Cortus SAS
Instructions are 16, 24 and 32 bits in length and the three-stage pipeline provides low power consumption and high performance while retaining a reasonable maximum clock frequency, Cortus claims. Out-of-order completion enables nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches. The processor was designed to execute high-level languages, notably C. The software application can be entirely realised in C, interrupt routines included. The entire GNU GCC tool suite has been ported to this architecture and is available free of charge.
The core delivers 2.83 Dhrystone MIPS⁄MHz and 1.44 CoreMarks⁄MHz in computational performance. The minimal usable APS23 CPU starts around 9.8 kgates when optimised for area. Dynamic power is 12 microwatts/MHz in a 90 nm process and Cortus cores are synthesizable and foundry independent.
"Cortus cores have a proven track record in low-power applications such as wireless, smart sensors and touchscreen controllers," said Michael Chapman, CEO of Cortus, "However, we know that today’s smart applications require a new generation of IP – IP designed with a minimalistic approach to system silicon area and power consumption while also providing good cost of ownership and key functionality. We have focused on reducing the size of the instruction memory which is usually the largest single component in a system and are seeing an average 16 percent improvement in code density over our earlier v1 cores."
The APS tool chain and IDE for C and C++ is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII.
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