Synopsys Inc. has introduced new DesignWare ARC HS5x and HS6x processor IP families for embedded applications.
The 32 bit ARC HS5x and 64 bit HS6x processors are implementations of a new superscalar ARCv3 instruction set architecture (ISA) and deliver up to 8750 DMIPS per core in 16 nm process technologies. The multicore versions include an interconnect fabric that links up to 12 cores and supports interfaces for up to 16 hardware accelerators. The processors can be configured for real-time operation or with an advanced memory management unit (MMU) that supports symmetric multiprocessing (SMP) Linux and other operating systems.
The new ARC HS processors are designed to meet the power and performance requirements of a broad range of embedded applications such as solid-state drives (SSDs), automotive control and infotainment, wireless baseband, wireless control and home networking.
The processors feature a high-speed 10-stage, dual-issue pipeline that offers increased utilization of functional units with a limited increase in power and area. The HS5x processors feature a 32 bit pipeline that can execute all ARCv3 32 bit instructions, while the HS6x processors feature a full 64 bit pipeline and register file that can execute both 32 bit and 64 bit instructions.
The processor IPs are supported by the ARC MetaWare Development Toolkit that includes an advanced C/C++ compiler optimized for the processors’ superscalar architecture, a multicore debugger to debug and profile code as well as a fast instruction set simulator (ISS) for pre-hardware software development.
