One thing was conspicuous by its absence in the materials that accompanied this week's launch of Imagination Technology Group's P5600 processor: a big-little strategy similar to that of rival ARM Holdings.
Although the Cortex-A15 from ARM was not mentioned explicitly, it appears that Imagination is trying to pitch the P5600, which is positioned as an application processor engine, at around or slightly better than the A15's performance level. But big-little has been a fundamental part of the roll out of ARM's highest performance 32-bit processors (Cortex-A15 and Cortex-A7) and its coming generation of 64-bit capable cores (Cortex-A57 and Cortex-A53).
Like the Cortex-A15, the MIPS P5600 has an extended physical address space that goes to 40-bits. Like the Cortex-A15 the P5600 has a 128-bit wide single-instruction multiple data (SIMD) extension.
Processor cores are such complex things that they can never be a simple drop-in replacement for their predecessors—unless they are architectural clones. However, Imagination's P5600 clearly goes some way to try and superset what developers may be used to from ARM—but not with regard to a big-little option.
Big-little is the approach pioneered by ARM, and picked up by some licensees, whereby differently optimized cores implementing the same instruction set architecture are deployed in an SoC to achieve superior energy-efficiency. The big core is optimized for peak performance, while the little core is optimized for energy efficiency. Tasks can be assigned to different cores, or moved between cores, depending on the power budget.
The net result is that ARM has shown how to trade off improved overall energy efficiency against slightly increased die area and cost.
The difference in power consumption and die area between the Cortex-A15 and Cortex-A7 is significant. The Cortex-A15 occupies about five times the area of the Cortex-A7 consumes about fives times the power while providing only two or three times the performance.
So why no big-little for Imagination's P5600?
"Big-little is one of a number of ways to construct a low-power CPU subsystem," said Mark Throndson, director of processor technology marketing at Imagination, in an email exchange. "Imagination’s cores are smaller and more efficient than the competition’s, and some of the leading SoC manufacturers, including ARM licensees do not incorporate big-little as part of their low power strategy. Many have implemented alternative schemes to avoid the associated complexity and overhead. With the P5600 CPU, Imagination offers a coherent cluster configuration with up to six cores in a cluster, allowing for a variety of performance/power configurations with less duplication and complexity."
The six cores are supported through a coherency manager and L2 cache controller, and the Throndson's comments with regard to varying performance and power are significant. It implies that a P5600 processor could be designed with a three or four cores optimized to operate at maximum clock frequency—say 2 GHz in 28-nm CMOS—while two or three would be designed for minimum current leakage and maximum power efficiency but with a maximum clock frequency that would top out at a few hundred megahertz. Indeed one could imagine a 4-plus-2 processor, or other combinations, based on the arrangement.
Imagination provides the P5600 as fully synthesizable RL with reference floor plans and implementation flows to help licensees. The company will likely provide routes to different performance points.
It may not be the same as a big-little strategy, and may not produce such extreme differences, but it would be a low-power/high-performance strategy that could satisfy many licensees' requirements, and possibly with less complexity.
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