Processor IP licensor ARM Holdings plc (Cambridge, England) announced it has defined an upgrade to its instruction-set architecture that aims to deliver increased performance while maintaining low latency and strong determinism for applications in automotive and industrial applications.
The ARMv8-R architecture follows on from ARMv7-R—the basis of ARM's current generation of real-time cores Cortex-R4, Cortex-R5 and Cortex-R7—and sits in parallel with the ARMv8-A, which was announced in 2011. ARMv8-A is the base of the development of 32- and 64-bit capable cores such as Cortex-A57 and Cortex-A53.
For now, ARMv8-R is aimed at 32-bit implementations, although 64-bit is not precluded, according to Chris Turner, senior product marketing manager. "It is probable that at a later date there will be a 64-bit addition but for now we support the AArch32 execution state," said Turner. Backwards compatibility is maintained with ARMv7-R and Thumb instruction sets so that legacy code can run.
Hypervisor and memory protection
The key innovation in ARMv8-R is support for a "bare metal" Hypervisor mode which enables programmers to "consolidate" different operating systems, applications and real-time tasks on a single processor. This is a so-called Type-1 hypervisor, as opposed to a type-2 or software only hypervisor, which does not support deterministic real-time operation. At the same time, it is expected that embedded applications will rely on multicore chips. The ARMv8-R also provides support for embedded programming techniques that are migrating towards model-based automated code generation, the company said.
Typical applications for ARMv8-R cores could include driver assistance systems and vehicle-to-vehicle communications in the automotive sector. In factory automation, a Cortex-R based chip could be responsible for managing critical tasks with real-time safety issues and human-machine interface control.
This could imply the co-existence of Linux or Android with real-time operating system and to support that ARMv8-R permits the use of both virtual memory and protected memory schemes. The improved memory protection scheme includes special measures to reduce context-switching time.
In order to maintain determinism, the stage-2 memory translation scheme of the ARMv8-R architecture differs from that of ARMv8-A. A conventional scheme would support translation at stage-2 so that every memory address produced at exception level 1 would be translated to a new address by a second stage of translation. In ARMv8-R the stage-2 scheme only supports protection and as a result the intermediate physical address generated by a given guest OS is always the same as the final physical address. The memory protection unit is register-based and tightly coupled to the processor, providing fast, deterministic responses. This avoids cases where an interrupt is not serviced in the required time due to the overhead of page-table walks required to refill the translation look-aside buffer (TLB) in the event of a cache miss.
The stage-2 MPU helps maintain the integrity of the hypervisor software and isolates each of the guest operating systems to its own physical address space, controlling whether or not a particular OS can assess any given peripheral or memory location.
ARMv8-R also implies an enhanced interrupt request controller. The mapping of interrupt control to system registers improves interrupt response time by removing the need for memory transactions to be performed in order to determine which interrupt pin caused the interrupt exception to be taken. The addition of a dedicated system error interrupt (SEI) provides a means of handling critical system errors.
Instructions carried over from the ARMv8-A architecture such as cyclic redundancy check for use in detecting the corruption of program code or data and support for NEON, ARM's approach to single-instruction, multiple data (SIMD) processing.
How quickly a new generation of Cortex-R cores will be developed remains unclear, but the expectation is that ARM cores compliant with ARMv8-R will be announced in 2014, with chips based on those cores coming in the second-half of 2015. "We'll be able to say more about ARMv8-R compliant chips in 2014," said Richard York, vice president of embedded systems marketing at ARM.
York said that first implementation would likely be aimed at the 45/40-nm node. "Most of these products require embedded flash memory and that is about as far as foundries can push it. No doubt a non-volatile memory solution will eventually come at 28-nm," he said.
Not surprisingly, ARM is working internally and externally to bring up support for design around cores based on ARMv8-R. The DS-5 ARM tools and Fast Models already support the ARMv8-A architecture, and support for the ARMv8-R architecture will be available to lead partners in 3Q14, ARM said.
Operating system companies working with ARM on the project include Green Hills Software, Mentor Graphics and eSOL. ARM and these partners have end applications in mind and integrated hardware and software solutions will be capable of supporting automotive and industrial interoperability and safety standards, including Autosar, ISO 26262 and IEC 61508, ARM said.
"We expect our eT-Kernel real-time OS and its dedicated IDE to be certified for ISO 26262 automotive functional safety standard in the second quarter in 2014," said Hiroaki Kamikura, general manager of eSOL's Embedded Products division, in a statement issued by ARM.
Details of ARMv8-R are set to be disclosed in at least a couple of presentations at ARM TechCon, which is due to take place in Santa Clara, Calif., Oct. 29 to 31. A white paper containing details of the new architecture can be found here.
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