Semiconductor Value Chain

Synopsys Offers IP Subsystem for Sensor Integration in SoCs

04 August 2013

Pre-integrating sensor-specific IP blocks with an efficient processor and software in a single subsystem is a must as more applications, such as the Internet of Things (IoT), automobile and mobile device markets increasingly rely on the ability to read and interpret environmental conditions such as pressure, temperature, motion and proximity.

As a result, the demand of sensors is exploding with estimates of sensor unit growth projected to rise from just under 10 billion in 2012 to nearly 30 billion in 2017, according to industry estimates.

To capture this growth, Synopsys, Inc. announced the availability of its DesignWare Sensor IP Subsystem, a complete and integrated hardware and software solution for sensor control applications.

The IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.

The DesignWare Sensor IP Subsystem provides designers with a complete and pre-verified solution that meets the requirements of a broad range of applications such as smart sensors, sensor fusion and sensor hub.

The Subsystem is based on the DesignWare ARC EM4 32-bit processor core and includes multiple configurable GPIO, SPI and I2C digital interfaces for off-chip sensor connections as well as ARM AMBA AHB and APB protocol system interfaces to ease integration into the full SoC.

The analog interfaces include ADCs that digitize sensor data for the processor. An FPGA-based prototyping solution enables immediate software development and provides a scalable platform for rapid full system integration and validation.

“As the technology leader in magnetic sensor ICs for the automotive market, it is critical that Allegro acquires high-quality IP from a trusted provider such as Synopsys,” said Robert Fortin, director of sensors business unit at Allegro Microsystems, LLC. “Based on our experience, the DesignWare ARC 32-bit processor’s combination of high performance, small area and low power provides key advantages for sensor design over alternative solutions.”

The DesignWare Sensor IP Subsystem offers a library of DSP functions enable a complete sensor subsystem to be configured in hours instead of weeks, according to John Koeter, vice president of marketing for IP and systems at Synopsys. The DesignWare Sensor IP Subsystem is targeted for availability in October 2013 to early adopters, with general availability planned for Q4 2013.

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