Electronics and Semiconductors

Synopsys Introduces Dual-Core Lockstep IP for Automotive SoCs

08 March 2017

Synopsys Inc. has unveiled a series of intellectual property (IP) dual-core lockstep processors designed to accelerate the development of automotive system-on-chips (SoCs).

The DesignWare ARC EM Safety Island IP are ASIL D ready IP processors that integrate a self-checking safety monitor as well as hardware safety features such as error correcting code (ECC) and a programmable watchdog timer to help detect system failures and runtime faults.

The dual-core lockstep IP processors offer enhanced safety features for development of automotive SoCs. Source: Synopsys  The dual-core lockstep IP processors offer enhanced safety features for development of automotive SoCs. Source: Synopsys The IP cores are designed to cover a broad range of automotive applications, including advanced driver assistance systems (ADAS), radar and sensors. The cores are configurable and extendable to meet the performance, power and safety requirements in automotive SoCs.

The dual-core lockstep processors are based on the 32-bit ultra-compact ARC EM4 processor with single-cycle closely coupled memories. The cores add more than 150 digital signal processor (DSP) instructions and a unified multiply/MAC unit to accelerate signal processing algorithms, Synopsys says.

Other options to the ARC EM Safety Islands include a floating point unit (FPU), a microDMA controller as well as a memory protection unit (MPU) for protection against malicious or misbehaving code in critical applications.

Synopsys says the cores can also operate in an independent dual-core mode to provide additional performance in applications that don’t need lockstep execution, such as those targeting ASIL B safety standards.

To contact the author of this article, email PBrown@globalspec.com


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