Semiconductor Equipment

Lam provides a path toward 1,000-layer 3D NAND flash

06 August 2024
An artist rendering of a 1,000-layer 3D NAND flash. Lam’s Cyro 3.0 dielectric etch technology is designed to get to this next-generation memory. Source: Lam Research

Lam Research Corp. has rolled out its third-generation cryogenic dielectric etch technology designed to provide a path to 1,000-layer 3D NAND flash technologies.

Called Cryo 3.0, the technology provides etch capabilities for the manufacturing of next-generation 3D NAND memory using cold temperatures, high power confined plasma reactor technology and advances in surface chemistry.

Currently, 3D NAND has advanced through the stacking of vertical layers of memory cells that are enabled through etching deep and narrow high aspect ratio (HAR) memory channels. Cryo 3.0 is designed to scale the challenges that memory OEMs have run into using this infrastructure.

“With five million wafers already manufactured using Lam cryogenic etch, our newest technology is a breakthrough in 3D NAND production,” said Sesha Varadarajan, senior VP of global products group at Lam Research. “It creates HAR features with angstrom-level precision, while delivering lower environmental impact and more than double the etch rate of conventional dielectric processes. Lam Cryo 3.0 is the etch technology our customers need to overcome the AI era’s key NAND manufacturing hurdles.”

How it works

The confined plasma reactors, process improvements and cold temperatures allow the harnessing of new, etch chemistries. Using Cryo 3.0 combined with pulsed plasma technology, both etch depth and profile control is significantly increased, Lam Research said.

Using Lam Cryo 3.0, 3D NAND OEMs can etch memory channels with depth of up to 10 microns with less than 0.1% deviation in critical dimension from the top to the bottom, Lam said.

Other features of the technology include:

  • 40% reduction in energy consumption per wafer
  • 90% reduction in emissions compared to other etch
  • Etches 2.5 times faster
  • Better wafer-to-wafer repeatability
To contact the author of this article, email PBrown@globalspec.com


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