A quartet of electronic design automation (EDA) vendors have made available reference flows for Intel Foundry’s embedded multi-die interconnect bridge (EMIB) packaging technology and process technology.
Ansys, Cadence, Siemens and Synopsys already declared readiness for Intel 18A designs and the reference designs will allow users to access Intel’s process and packaging technologies. This includes manufacturing semiconductors like system-on-chip designs with validated EDA tools, design flows and intellectual property (IP) portfolios for silicon-through-package design.
As the semiconductor industry moves into the heterogeneous era where the use of multiple chiplets in a package becomes the norm, Intel’s Foveros and EMIB packaging technologies offer a more efficient path toward 1 trillion transistors on a chip. This will also help extend Moore’s Law beyond 2030, Intel said.
Intel believes that its advanced packaging technology, which it has heavily invested in for years, will set it apart from other foundries and offer an advantage other foundries may not have.
Mixed integration allows engineers to have more control over features and functions of the products. Mixing and matching features by selecting multiple dies with required IP is a challenge that packaging may be able to help with and what Intel is working toward.
EMIB simplifies the design process with flexibility that can still develop advanced architectures like Intel’s GPU Max series and its latest Xeon processors.
The announcements include:
- Ansyss’ signoff verification of thermal, power integrity and mechanical reliability for EMIB
- Cadence’s complete EBID 2.5D packaging flow
- Siemens EMIB reference flow
- Synopsys’ AI-driven multi-die reference flow for EMIB
