Semiconductor Equipment

Video: Intel opens first mass production 3D chip packaging site

25 January 2024

Intel has opened its Fab 9 in Rio Rancho, New Mexico, which the company claims will be the first operational site for mass production of 3D packaging technology.

The opening of Fab 9 is part of Intel’s previously announced $3.5 billion investment to improve manufacturing and operations for packaging, including its Foveros 3D packaging technology.

Foveros is a 3D packaging technology that can offer the ability to combine multiple chips. The technology allows the building of processors with compute tiles stacked vertically, rather than side-by-side. Intel and its foundry customers can then mix and match compute tiles for better cost, power efficiency or both.

Additionally, Fab 9, along with Intel’s Fab 11x facility also in Rio Rancho, is the first co-located high-volume advanced packaging site. Something Intel said provides an end-to-end manufacturing process that creates an efficient supply chain from demand to final product.

The opening of Fab 9 will create hundreds of high-tech Intel jobs, 3,000 construction jobs and an additional 3,500 indirect jobs across New Mexico, Intel said.

Why it matters

Intel believes that its advanced packaging technology, which it has heavily invested in for years, will set it apart from other foundries and offer an advantage other foundries may not have.

As the semiconductor industry moves into the heterogeneous era where the use of multiple chiplets in a package becomes the norm, Foveros and embedded multi-die interconnect bridge (EMIB) technologies offer a more efficient path toward 1 trillion transistors on a chip. This will also help extend Moore’s Law beyond 2030, Intel said.

Mixed integration allows engineers to have more control over features and functions of the products. Mixing and matching features by selecting multiple dies with required IP is a challenge that packaging may be able to help with and what Intel is working toward.

This move away from monolithic silicon and toward an easier form of custom design allows companies to take ownership of SoC designs with these advanced packaging techniques.

To contact the author of this article, email PBrown@globalspec.com


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