Synopsys has achieved certification of its artificial intelligence (AI)-driven digital design and analog design flows on Samsung Foundry’s SF2 process.
The design flows boost productivity, accelerate analog design migration and enhance performance, power and area (PPA) for the foundry’s gate-all-around (GAA) process technologies. This is the same co-optimization techniques that will be applied to Samsung’s SF1.4 process.
Both companies collaborated on the AI-driven flows including Synopsys DSO.ai for design productivity and PPA optimization as well as Synopsys ASO.ai for analog design migration. Synopsys said this resulted in a new analog design migration reference flow using Synopsys ASO.ai for Samsung FinFET to GAA processes.
This enables designers to migrate Samsung 8 nm analog intellectual property to SF2 process and adding to Synopsys’ established flows on Samsung’s 14 nm to 8 nm/SF5 processes.
The AI-enabled tools are used to give chipmakers a way to reduce integration risk and acceleration time to silicon for:
- High performance computing
- Multi-die designs
- Mobile communications
- Automotive systems
Additionally, the tools will help to accelerate integration of chiplets in multi-die packages with the Synopsys UCIe IP taped out in SF2 and SF4x and achieved silicon success in SF5A process technologies. This helps to deliver robust die-to-die connectivity with low power and low latency.
