Siemens Digital Industries Software is collaborating with Siliconware Precision Industries Co. Ltd. (SPIL) to develop IC package assembly planning and 3D layout versus schematic (LVS) assembly verification workflow for advanced IC packaging technologies.
Outsources assembly and test (OSAT) vendor SPIL will deploy the software across its 2.5D and fan-out package family technologies.
The goal of the technologies is to meet the demand for more performance and lower power consumption in small footprint designs with complex packaging such as 2.5D and 3D configurations. The technology combines one or more ICs of different functionality with increased I/O and circuit density to create and review multiple assemblies and LVS, connectivity, geometry and component spacing scenarios.
SPIL will use Siemens’ Xpedition Substrate Integrator software and Calibre 3DStack software for package planning and 3D package assembly verification LVS in fanout packages.
“Our challenge was to develop and deploy a proven advanced packaging assembly planning and verification workflow that included comprehensive 3D LVS,” said Yu Po Wang, vice president of CRD at SPIL.
SPIL’s fan-out packaging family offers additional space for routing a higher number of I/O on top of the semiconductor’s area and extending the package size with a fan-out process, which cannot be achieved with conventional advanced packaging technologies, the companies said.
