The Tessent multi-die software solution from Siemens Digital Industries Software helps customers dramatically speed and simplify critical design-for-test (DFT) tasks for next-generation integrated circuits (ICs) based on 2.5D and 3D architectures.
As demand for smaller, more power efficient and higher performing ICs continues to challenge the global IC design community, next-generation devices increasingly feature complex 2.5D and 3D architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so that they behave as a single device. However, these
Source: Siemens Digital Industries Software approaches can present significant challenges for IC test, since most legacy IC test approaches are based on conventional two-dimensional processes.
Source: Siemens Digital Industries Software approaches can present significant challenges for IC test, since most legacy IC test approaches are based on conventional two-dimensional processes.To address these challenges, Siemens developed Tessent multi-die software as a comprehensive DFT automation solution for highly complex DFT tasks associated with 2.5D and 3D IC designs. The new solution works seamlessly with Siemens’ Tessent TestKompress Streaming Scan Network software and Tessent IJTAG software, which optimize DFT test resources for each block without concern for impacts to the rest of the design, thereby streamlining DFT planning and implementation for the 2.5D and 3D IC era. Using Tessent multi-die software, IC design teams can rapidly generate IEEE 1838 compliant hardware featuring 2.5D and 3D IC architectures.
The die solution can also generate die-to-die interconnect patterns and enable package level test using the Boundary Scan Description Language (BSDL). Further, Tessent multi-die supports integration of flexible parallel port technology by leveraging the packetized data delivery capabilities of Siemens’ Tessent TestKompress Streaming Scan Network software. Introduced two years ago, Tessent TestKompress Streaming Scan Network decouples core-level DFT requirements from the chip-level test delivery resources. This enables a no-compromise, bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to four times.
