Electronic Design Automation

UMC certifies Cadence’s advanced 3D EDA tech for chipmaking

02 February 2023

Pure play foundry United Microelectronics Corp. (UMC) has announced that Cadence Design Systems’ 3D-IC reference flow has been certified for UMC’s chip stacking technologies.

UMC said its hybrid bonding solutions are now ready to support the integration across a broad range of technology nodes that can be suitable for edge AI, image processing and wireless communication applications.

Both companies collaborated to validate key 3D-iC features including system planning and intelligent bump creation using UMC’s 40 nm low power process as a wafer-on-wafer stacking demonstration. UMC said this is the first comprehensive solution that integrates system planning, chip and packaging implementation and system analysis in a single platform.

“Interest in 3D-IC solutions has increased notably in the past year as our customers seek ways to boost design performance without sacrificing area or cost,” said Osbert Cheng, vice president of device technology development & design support at UMC. “Cost-effectiveness and design reliability are the pillars of UMC’s hybrid bonding technologies, and this collaboration with Cadence provides mutual customers with both, helping them reap the benefits of 3D structures while also accelerating the time needed to complete their integrated designs.”

The platform

The 3D-IC reference flow, which features Cadence’s Integrity 3D-IC platform, is built around high-capacity, multi-technology hierarchical database for design planning, implementation and analysis of full 3D designs in a single unified cockpit.

Multiple chiplets in a 3D stack can be designed and analyzed together through integrated early analysis for thermal, power and static timing analysis. The flow enables system-level layout versus schematic (LVS) checking to connectivity accuracy, electric rule-checking for coverage and alignment checking.

Additionally, the Integrity 3D-iC platform includes:

  • Innovus implementation system
  • Quantus extraction solution
  • Tempus timing signoff solution
  • Pegasus verification system
  • Voltus IC power integrity solution
  • Celsius thermal solver for system analysis
To contact the author of this article, email PBrown@globalspec.com

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