Electronic Design Automation

Synopsys launches complete HBM3 IP and verification system

12 October 2021

Electronic design automation (EDA) vendor Synopsys Inc. has introduced what it claims is the first complete Rambus High-Bandwidth Memory generation 3 (HBM3) intellectual property (IP) solution.

The system includes a controller, PHY and verification IP for 2.5D multi-die package systems.

HBM3 is a high-performance memory from Rambus that features reduced power consumption and a small form factor. When combined with 2.5D packaging with a wider interface at a lower clock speed, it delivers higher throughput at a higher bandwidth-per-watt efficiency for artificial intelligence (AI) and machine learning and high-performance computing applications.

The DesignWare HBM3 Controller and Phy IP, built on silicon proven HBM2E IP, enables high memory bandwidth at up to 921 GB/s.

The HMB3 solution includes verification IP with built-in coverage and verification plans, off-the-shelf HMB3 memory models for ZeBu emulation and HAPS prototyping system, accelerating verification from HBM3 IP to system-on-chips. The Synopsys 3DIC Compiler multi-die design platform provides an integrated architectural exploration, implementation and system-level analysis solution.

The DesignWare HBM3 Controller IP supports a variety of HBM3-based systems with flexible configuration options and minimizes latency and optimizes data integrity with advanced RAS features such as error correction code, refresh management and parity.

The system is available in 5 nm processes as pre-hardened or customer configurable PHY, operates at up to 7200 Mbps per pin to improve power efficiency and supports up to four active operating states for dynamic frequency scaling. The software also uses optimized micro bump arrays to minimize area and support for interposer trace lengths for flexibility in PHY placement.

To contact the author of this article, email PBrown@globalspec.com


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