Electronic Design Automation

First demonstration of interoperability of PCIe 6.0 IP

20 September 2023

Synopsys Inc. has achieved what it claims is the first demonstration of end-to-end 64 GT/s interoperability between the company’s intellectual property (IP) for PCI Express (PCIe) 6.0.

The test was done using Intel Corp.’s 6.0-enabled test chip that will allow designers to reduce risk and accelerate time to market.

The demo showed the interoperability between Synopsys endpoint PHY and controller IP for PCIe and the PCIe 6.0 test chip. Synopsys offers a solution for PCIe 6.0 that includes controllers, PHYs, verification IP and integrity and data encryption (IDE) security IP.

"To meet the demands of data-intensive operations in the cloud and on the edge, designers require advanced connectivity and processing technologies that operate with low latency at fast speeds," said Debendra Das Sharma, senior fellow and co-GM of memory and I/O Technologies at Intel. "Our intent with this demonstration is to give the ecosystem confidence that Intel's future generation products with PCIe 6.0 will be interoperable with the ecosystem, enabling broad adoption of the PCIe 6.0 standard."

To contact the author of this article, email GlobalSpecEditors@globalspec.com

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