Synopsys Inc. has expanded its hardware-assisted verification (HAV) portfolio with HAPS prototyping and ZeBu emulation systems using AMD’s Versal Premium VP1902 adaptive system on chip (SoC).
The Synopsys Emulation and Prototyping (EP-Ready) hardware enables emulation and prototyping use cases via reconfiguration and optimized software. ZeBu Server 5 can deliver scalability beyond 60 billion gates to address hardware and software complexity in SoC and multi-die designs.
Synopsys said as the industry approaches hundreds of billions of gates per chip and hundreds of millions of lines of software in SoCs, verification of design poses new challenges. The HAV expansion is designed to meet these growing complex design challenges, the company said.
The expansion
The HAPS-200 prototyping system offers runtime performance and faster compile with four times improved debug performance over the previous generation. It also uses the same ecosystem and supports mixed HAPS-200/100 system from single field programmable gate array (FPGA) to multi-rack setups with capacity of up to 10.8 BG.
The ZeBu-200 emulation system offers up to two times higher runtime performance versus the previous generation with faster compilation time to reduce turnaround time and enhanced development productivity. It also features up to eight times better debug bandwidth, offering 200 GB debug trace memory per module and improved job scheduling and relocation.
