A new dynamic random-access memory (DRAM) verification solution developed by Cadence Design Systems Inc, will allow customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. Using the full DRAM verification solution, which delivers up to 10 times increased verification throughput, customers can quickly and effectively perform intellectual property (IP)-to-SoC-level verification of advanced designs with multiple double data rate (DDR) interfaces.
Modern SoC designs leverage advanced memory technologies, such as low-power DDR5x, DDR5, high bandwidth memory (HBM) 3 and graphics DDR 6, which require rigorous verification at the PHY and IP levels to ensure compliance with the JEDEC standard as well as SoC-level verification to meet application-specific system performance definitions and data and cache coherency requirements.
The new DRAM verification solution enables IP-level verification through Cadence PHY VIPs and memory models with a direct and seamless path to SoC-level verification with the Cadence System VIP solution, including the System Performance Analyzer, System Traffic Libraries and System Scoreboard, all with built-in integration and content for DRAM interfaces, enabling fast and efficient memory subsystem and SoC verification for simulation and emulation environments.
The solution also includes Cadence TripleCheck technology, which provides users with a verification plan linked to a specification, including JEDEC, DFI and PHY, comprehensive coverage models, and a test suite to ensure compliance with the interface specification.
