Mentor Graphics Corporation, a Siemens business, has announced Tessent Connect, a new design-for-test (DFT) methodology that enables IC designers to hit manufacturing test goals faster and with fewer resources than traditional DFT methods.
Tessent Connect was designed to support intent-driven hierarchical test implementation. Hierarchical DFT methodology divides a chip design into submodules and runs tests on these modules in parallel. This approach saves time and avoids the inefficiencies of a flat test layout. Retrofitting existing DFT tools to a hierarchical design produces new inefficiencies, negating this method’s advantages.
With the increasing size of chip designs and of the memory instances within designs, a faster but still accurate methodology is desirable. IC designers interact with Tessent Connect design tools at a higher level of abstraction than non-hierarchical tools. Advantages of this approach include the following:
- Seamless collaboration across different DFT teams
- Plug-and-play reuse of components
- Shorter turn-around times
- Automation of time-consuming tasks
The Tessent Product Suite includes automotive, memory test, silicon learning, logic test and mixed-signal test components. Additional information is available from the company.
