As integrated circuit designs continue to grow in both size and complexity, it becomes increasingly important to identify and address testability issues at the earliest possible stages — a principle sometimes referred to “shift-left testing.”
That concept is exemplified by Siemens’ Tessent portfolio of silicon lifecycle solutions, which enables the analysis and insertion of a large majority of design-for-test (DFT) logic early in the design flow. By performing quick synthesis and then running automatic test pattern generation (ATPG), Tessent identifies outlier blocks so that appropriate measures can be taken.
A new entry to Siemens’ Tessent portfolio of silicon lifecycle solutions evaluates whether a register transfer level structure can be efficiently edited. Source: Siemens Digital Industries SoftwareEarlier this month, Siemens announced RTL Pro, an extension of the Tessent portfolio that automates the early analysis and insertion of test points, wrapper cells and x-bounding logic. The software analyzes register transfer level (RTL) complexity and its adaptability for test point insertion, evaluating whether an RTL structure can be efficiently edited — a critical factor when adding test points throughout the design. This, in turn, supports improved testability, reduced design turnaround time and better time-to-market.
For a case study in the successful implementation of the new software, Siemens cites semiconductor company Renesas. “Adopting Tessent RTL Pro for our next-generation automotive semiconductor design allows us to extend our shift-left strategy and reduce the iterations of the conventional design flow,” said Tatsuya Saito, a senior electronic design automation engineer with the company. “The ability to provide our back-end and verification teams with the same, complete design view containing all Tessent IP, including VersaPoint test points in RTL, is paramount for our competitiveness.”
Unlike competing solutions, according to Siemens, Tessent RTL Pro handles complex Verilog and SystemVerilog constructs while maintaining the look and feel of the original RTL design. The software’s “shift-left” functionality also helps enhance the ability of third-party tools to optimize area and timing when adding DFT logic prior to synthesis. Design insertion happens at the development stage, with RTL output, allowing seamless integration with third-party synthesis and verification software. Because the generated design files will work with any downstream synthesis or verification flows, Siemens adds, a closed-flow process is not required.
Click here for a white paper on Siemens’ Tessent silicon lifecycle solutions.
