A pair of recent announcements from Siemens Digital Industries Software speak directly to teams working on integrated circuit design and manufacturing.
First, the new Tessent Hi-Res Chain tool, part of the company’s Tessent portfolio of silicon lifecycle management solutions, which considers the challenge of advanced node geometries of 5 nm and below. As designs progress into this level, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. Even for minor process variations, traditional failure analysis methods can require weeks or months of laboratory effort to investigate.
The new Tessent tool provides rapid transistor-level isolation for scan chain defects, boosting diagnosis resolution by more than 1.5 times and reducing the need for costly extensive failure analysis cycles. By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), the software transforms failing test cycles into actionable insights.
According to Siemens, the solution employs layout-aware and cell-aware technology to pinpoint a defect's most probable failure mechanism, logic location and physical location.
Then there’s a new fully automated solution designed to help IC design teams rapidly identify and address electrostatic discharge (ESD) issues driven by the growing complexity of next-generation designs, regardless of the targeted process technology.
Siemens said foundry ESD rules are designed to prevent ESD failures, while accommodating the diverse design styles submitted by fabless companies globally. Yet these rules may be overly conservative for specific design styles and mission profiles. Combining the power of the company’s Calibre PERC software with the SPICE accuracy of its AI-powered Solido Simulation Suite, the new solution can rapidly identify and simulate ESD paths that might fail foundry rules with detailed transistor-level breakdown models. This paves the way for fast, targeted and automated fixes, allowing design teams time to secure waivers from foundry rules that can allow them to work with smaller die sizes and optimized designs.
Automated context-aware IC design verification can now become a best practice, Siemens continues, helping the quick delivery of reliable and timely IC chips to market. Featuring functionalities such as automated voltage propagation, voltage-aware design rule checking, and the integration of physical and electrical information within a logic-driven layout framework, the new solution helps design teams working to tight schedules.