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SEMICON West 2018: Imec and Soitec Demonstrate Sequential 3D Planar Device with High Reliability at Low Temperature

10 July 2018

Imec, in collaboration with Soitec, announced a successful sequential 3D front-end integration process by stacking two device layers on one another on a 300 mm wafer. The debut occurred at the annual Imec Technology Forum USA.

This vertical integration process, also named sequential-3D integration (S3D), promises to continue the benefits offered by semiconductor scaling, overcoming the constraints of geometrical scaling while maintaining the benefits of functional scaling through the vertical 3D integration.

A critical challenge of S3D is the control of the thermal budget. To preserve optimal device operation the top device layer must be processed at temperatures below 525° C. The top thermal budget needs to be reduced to avoid degradation of the bottom devices, the bottom interconnects and the bonding interface. These limitations are overcome with the implementation of junction-less transistors on the top-layer which decreases the fabrication complexity and provides sufficient device reliability.

“Demonstrating a good performance of the top-tier device using a low-temperature process is an important breakthrough in our aim to develop sequential 3D as a valid option to further increase power-performance-area-cost in advanced technology nodes beyond 5nm,” stated Anne Vandooren, senior researcher at Imec. “To realize this, we had to use very advanced technologies in some of the most critical process steps including back-end-of-line, contacts, and gate stacks.”

Bich-yen Nguyen, senior fellow at Soitec adds, “This exciting R&D collaboration between imec and Soitec is paving the way for global innovation. Together we are leveraging the maturity of Soitec’s Smart Cut™ process, excellent quality and thickness control, and imec’s advanced device and integration know-how, to develop another method to meet the PPAC (Power, Performance, Area and Cost) in scaling.”

Figures 1 and 2 show performance results of the structure.

Figure 1: TEM cross-section of the 3D structure showing (left) stacked top and bottom tier devices with nanometric alignment, (center) 3D contacts to the bottom devices and (right) magnified top tier P and NMOS devices. Source: ImecFigure 1: TEM cross-section of the 3D structure showing (left) stacked top and bottom tier devices with nanometric alignment, (center) 3D contacts to the bottom devices and (right) magnified top tier P and NMOS devices. Source: Imec

Figure 2: This chart displays the reliability improvement of junction-less devices (JL) over inversion mode (IM) devices processed at low temperature. Data of optimized FinFETs with high temperature reliability anneal are reported as a reference. Depicted here are NBTI and PBTI VT shifts (DVth) measured at VG=Vth0+0.6V, T=125° C, at a stress time of 1000 s, and a sense time of 1 ms. Source: ImecFigure 2: This chart displays the reliability improvement of junction-less devices (JL) over inversion mode (IM) devices processed at low temperature. Data of optimized FinFETs with high temperature reliability anneal are reported as a reference. Depicted here are NBTI and PBTI VT shifts (DVth) measured at VG=Vth0+0.6V, T=125° C, at a stress time of 1000 s, and a sense time of 1 ms. Source: Imec

To contact the author of this article, email abe.michelen@ieeeglobalspec.com


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