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Power-Aware Architecture Analysis Tool Supports IEEE 1801-2015 UPF 3.0

28 January 2016

Synopsys’ Platform Architect with Multicore Optimization. (Source: Synopsys)Synopsys’ Platform Architect with Multicore Optimization. (Source: Synopsys)

Synopsys Inc. has announced that its Platform Architect with Multicore Optimization virtual prototyping solution is reportedly the first to support the new IEEE 1801-2015 Unified Power Format (UPF) 3.0 system-level IP power modeling standard. The standard enables efficient creation and reuse of interoperable IP power models for early analysis of power and performance for multicore SoC architectures.

Combined with Platform Architect MCO's native support for IEEE 1666-2011 System transaction-level modeling (TLM) and Synopsys' Fast Timed (FT) model library, architects gain a unified view of system activity, performance and power to accelerate power-aware architecture design for multicore Socks months earlier in the development cycle.

A system-level IP power model is an abstraction of the power behavior of a component that provides a specification of its power states and the associated power consumption data for each state. These abstracted power models enable early analysis of system-level power budgets and can be refined as more specific implementation information becomes available.

To understand the impact of power management on system performance, architects and system designers must analyze power together with the simulation of realistic application workloads. Platform Architect MCO and its library of Fast Timed power aware architecture models provide this unified view based on fast simulation, quantitative analysis results and the ability to add power models without change. Together, this enables the efficient optimization of dynamic voltage frequency scaling (DVFS) power management policies and the partitioning of Sock power domains months before the complete RTL system is available.



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