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The Growing Importance of Verification in Chip Design

26 April 2016

Design Verification.


Trust, but Verify.


That famous phrase from the era of Cold War diplomacy has particular relevance now in electronic design automation (EDA), where the validation and verification process is gaining increased importance for chips going into automotive vehicles, medical equipment, military and aerospace systems, and Internet of Things products.


International standards, such as ISO 26262 for autos, are creating new requirements for documentation and traceability in chip design. Such standards require all suppliers of parts to show how they conceived, designed and manufactured those parts in order to identify any breakdowns in functional safety and security (including cybersecurity in these hacker-afflicted times).


As a result, verification is growing in significance to meet those new demands. Simulation and emulation technology is being enhanced to help accelerate validation and verification tasks.


Wally Rhines, chairman and chief executive officer of Mentor Graphics Wally Rhines, chairman and chief executive officer of Mentor Graphics While the compound annual growth rate for design engineers is 3.7 percent, verification engineers are enjoying a CAGR of 12.8 percent, according to Wally Rhines, chairman and chief executive officer of Mentor Graphics.


“Verification complexity grows three to four times the rate of design creation,” he said in March at the annual Design and Verification Conference (DVCon). Verification for security and safety issues involves “separating the what from the how,” he added.


Now it is crucial for engineers to be “verifying a chip does nothing it is not supposed to do,” Rhines said in his keynote address, "especially given the volume of semiconductor intellectual property blocks that typically go into an integrated circuit design these days. That IP is drawn from multiple sources, and it all has to be 'clean,' not containing any malicious code," he noted.


For medical equipment, the relevant standard is IEC 60601, and it is DO-254 for military and aerospace systems, Rhines said.
Stephen Bailey, Mentor’s director of emerging technologies, spoke at DVCon about issues in verification. Debugging a design can now take up to 37 percent of the chip design timeline, he said, adding, “Debugging is not fun.”


Mentor and other EDA vendors are working to improve verification productivity, Bailey said, which causes many engineers to say, “It’s about time!” Engineers are eager to avoid getting stuck in “debug iteration hell,” he added. Mentor offers the Veloce2 Emulation Platform and the Questa Verification line, among other tools.


Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group within Cadence Design Systems, discussed verification issues in a keynote presentation at the company’s CDNLive Silicon Valley conference in April.

om Beckley, senior vice president and general manager of the Custom IC & PCB Group within Cadence Design Systems  om Beckley, senior vice president and general manager of the Custom IC & PCB Group within Cadence Design Systems
“Software needs to be organized in functional modules,” he said. “Software is very malleable. How do you architect for vulnerability?”
Beckley emphasized the concept of functional safety in his talk. “Smartphones are a system of systems,” he noted, and autos are similar in how they’re designed and made. A standard vehicle can contain 100 million lines of software code, heightening the requirement for verification and functional safety, according to Beckley.


“This is all before hackers attack,” he commented. “You have to comply with dozens of standards. System-level defects are the most troubling.”


Beckley went on, “This is the world of the Internet of Things, hardware and software co-development. Software, verification and validation are dominating the cost of system-on-a-chip devices.”


There are also 2.5-D and 3-D chip packaging, flexible printed circuit boards, and software’s power and thermal issues, he added. Plus, “85 percent of chips today have some mixed-signal [analog and digital] content.”


Beckley continued, “Our world is changing. We need to provide unified solutions.” EDA companies also need to consider “development of the software stack,” he said.


He later said in an interview, “Functional safety comes up now. Not four years ago.” Customers have a longer list of requirements to fulfill, and EDA vendors must accommodate them.


While Cadence has just refreshed its Virtuoso Analog Design Environment suite of tools, there are more challenges ahead in EDA, according to Beckley. “Radio frequency is the harder version of analog,” he said. “Interconnect is parasitic. Electromagnetics comes into it.”


Aart de Geus, the chairman and co-CEO of Synopsys Aart de Geus, the chairman and co-CEO of Synopsys Aart de Geus, the chairman and co-CEO of Synopsys, talked about the Internet of Things and related topics at his company’s user group meeting in late March. “Everything is going to become smarter,” he said.


Autonomous vehicles are one part of the equation. “There is no question; this is happening,” de Geus said of self-driving cars. “Auto companies are talking about FinFETs.”


Verification now calls for “the fastest engines, unified compile, unified debug,” he noted. Synopsys unveiled its VCS Cheetah simulator for SoC design just before the SNUG meeting, and de Geus talked up the product’s attributes in his keynote address.


These days in electronic system design, a lot of verification is needed before trust can be secured.



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