Three-dimensional devices are sure to be a hot topic in 2016. The key is to know what kind of 3D chips you’re talking about.
Stacked complementary metal-oxide-semiconductor (CMOS) image sensors already are a commodity product, with Sony dominating the market for such devices, which stack the pixel chip atop a logic integrated circuit.
Sony stacked CMOS image sensor.
Sony Semiconductor is spending about $1.25 billion to expand its production capacity for stacked CMOS image sensors from around 60,000 wafers per month to approximately 87,000 wafers per month by the end of September at its Nagasaki Technology Center and Yamagata Technology Center. Late last year, the company reached an agreement to acquire Toshiba’s 300-millimeter wafer fabrication facilities in Oita City, Japan, where CMOS image sensors and memory controller chips are made, for $157.8 million; about 1,100 Toshiba employees will transfer to Sony by the end of March.
Advanced 3D chip technology is coming to microelectromechanical system (MEMS) devices, as well as image sensors, according to industry analysts. “CMOS image sensors and MEMS are following the same path,” says Jean-Christophe Eloy, president and chief executive officer of Yole Développement. “Software is gaining in importance,” he adds.
The state of the art in 3D chip technology was explored at length at the annual 3D Architectures for Semiconductor Integration and Packaging (3D ASIP) conference, held last month in Redwood City, Calif.
Altera (now a business unit of Intel) and Xilinx executives offered their perspectives on pairing field-programmable gate arrays with other chips at 3D ASIP, put on by RTI International.
Organic substrates offer a slight improvement on standard 2D chip technology, while silicon interposers move the needle to 2.5D, according to Arifur Rahman of Altera. For 3D die stacking, there is Intel’s embedded multi-die interconnect bridge (EMIB) technology, which involves a more complex organic substrate, he says.
Altera Stratix 10.Altera’s Stratix 10 FPGAs and system-on-a-chip devices make use of heterogeneous 3D system-in-package (SiP) technology and HBM2 high-bandwidth memory DRAMs in the same package. Stratix 10 offers twice the performance of Altera’s Stratix V FPGAs, while reducing power consumption by up to 70%, Rahman notes.
The Stratix 10 line is aimed at applications in 8K video, finance, high-performance computing, networking, and radar systems, Rahman says.
One common theme of the 3D ASIP conference was providing alternatives to through-silicon vias (TSVs) in connecting chips stacked in a single package. “TSV is an expensive technology,” says Minsuk Suh of SK Hynix.
Suresh Ramalingam of Xilinx detailed his company’s Silicon-less Interconnect Technology (SLIT), developed with the help of Siliconware Precision Industries. SLIT is meant to connect multiple die in one package, without TSVs.
“Multi-die technology [has] been around for quite some time,” he says. He noted a famous IBM aphorism: “Big chips sink ships.”
Taiwan Semiconductor Manufacturing is “our primary partner in interposer technology,” Ramalingam says.
TSMC’s K. C. Yee spoke about fan-out wafer-level technology, a less expensive alternative to TSVs. The silicon foundry’s InFO offering “eliminates silicon, TSVs, interposers,” he says, while reducing manufacturing cost.
With InFO, there are no substrates or wafer bumping involved, according to Yee. The packaging technology provides “powerful and cool integration,” he adds, with direct dissipation of heat. It is also compatible with flip-chip packaging, Yee said.
Yole’s Thibault Buisson said 2015 was “a key year for TSV in memory. Memory will be the next segment to use TSV, after MEMS and CMOS image sensors.” The analyst notes, “Transistor scaling and cost reduction will not continue on the same path” as they have over the past five decades under Moore’s Law. Technologists need to focus now on “bridging the gap between silicon and printed circuit boards,” he adds.
Hybrid Memory Cube.Micron Technology, Samsung Electronics, SK Hynix, and Tezzaron Semiconductor are all offering DRAMs stacked in a package, employing TSV interconnections. Buisson sees DDR4, Wide I/O2, high-bandwidth memory, and Hybrid Memory Cube technology being used for graphics and high-performance computing in 2016, while adding networking applications in 2017.
NAND flash memory devices call for a 3D front-end approach, while DRAMs need a 3D back-end approach, the Yole analyst says. For NAND flash, planar scaling will stop at the 10-nanometer process node, he added.
2016 will see shipments of Nvidia’s Pascal graphics processing unit, which will incorporate four HBM2 memories for 16 gigabytes of data storage and bandwidth of 1 terabyte per second, Buisson noted.
Brandon Prior of Prismark Partners says silicon interposers, a 2.5D technology, are “the only effective solution today.” The industry needs to move on to “fully integrated solutions” in one to two years, he adds, with SiP and system-in-module packaging coming to the fore.
While the packaging technology in the new Apple Watch is touted as SiP, it actually is system-in-module technology involving wafer-level chip-scale packaging with “very aggressive geometries,” Prior says.
3DIC technology is on the march, with CMOS image sensors and memory devices leading the way. 2016 and following years will see how 3D chip technology spreads to other semiconductor segments.
