Field programmable gate array (FPGA) giant Xilinx Inc. has introduced a low-density parity check (LDPC) error correction intellectual property (IP) core to its portfolio in order to enable next-generation flash-based applications for cloud and data center storage.
LDPC error correction is considered a critical core function for meeting reliability and endurance requirements in storage solutions, Xilinx says. This is even a greater need with NAND flash advancing into 3D NAND technology. Xilinx’s error correction IP architecture is scalable, future-proof supporting various next-generation non-volatile memory devices, features a high throughput and low latency key for storage applications, the company says. The core also allows for less than 50% logic against alternative solutions.
The flash memory LDPC error correction IP is available now for early access with general availability to begin in the fourth quarter of this year.
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