The prospects for nanowire transistors based on compound semiconductors—a possible follow-on technology to FinFETs—has received a boost in a paper authored by IBM researchers based in Zurich, Switzerland, and Yorktown Heights, New York.
The team has developed a method to build nanowires and multi-gate transistors, from III-V compound semiconductors on top of silicon-on-insulator (SOI) wafers.
The world's major chip manufacturers have already decided upon the use of FinFETs at the 10nm node but development work for the next node has already begun with questions about transistor materials. The techniques being reported by IBM could be in demand at the 7nm or 5nm nodes.
Template-assisted selective epitaxy
The method is called template-assisted selective epitaxy (TASE) and the combination of semiconductor types is significant because III-V compound semiconductors have intrinsically higher electron mobility than silicon—which is related to switching speed and performance—but the silicon manufacturing ecosystem is more mature and allows economies of scale, such as manufacturing on 300mm diameter wafers in large wafer fabs. IBM claims to have made progress in trying to achieve this integration of compound and silicon processing in its paper published in the journal Applied Physics Letters.
Numerous previous attempts to address the crystal lattice mismatch between silicon as the carrier wafer and the III-V materials, such as compounds of indium, gallium and arsenide, are referenced in the paper but only as being partially successful. They have been accompanied by either the presence of significant crystal defects or have required extensive surface preparation and multi-step processing and therefore are costly, or have only been applicable to the creation of vertical structures.
Now, the IBM team claims to have made many of the lateral structures required to allow integration of compound semiconductors with silicon processing as an evolution of the FinFET. This single crystal nanostructures include nanowires, nanostructures containing constrictions, and cross-junctions, as well as 3D stacked nanowires.
The TASE technique uses lithography and reactive ion etching applied to an SOI wafer to predefine the structures required in a thin layer of silicon on top of the silicon-oxide insulator. The wafer then receives a 30nm-thick silicon oxide blanket, creating nanostructure templates defined in silicon and silicon oxide. These template structures are subsequently etched back to expose a silicon crystal plane that is well matched to the orientation of a particular compound semiconductor. Such a semiconductor is then deposited by metal-organic chemical vapor deposition (MOCVD). The first layers of compound semiconductor then act as the seed that allows much larger defect-free monocrystalline compound semiconductors to be grown, effectively filling in the oxide template with III-V epitaxy.
To demonstrate the technique, the research team has reported results for indium arsenide (InAs) nanowires measuring 95nm wide by 23nm thick, for Hall Effect structures measuring 50 microns wide by 20nm thick. InAs multigate FETs measuring 25nm wide and 23nm thick with an aluminum oxide gate over hafnium oxide high-k dielectric over titanium nitride were also fabricated and measured and found to perform well.
"What sets this work apart from other methods is that the compound semiconductor does not contain detrimental defects, and that the process is fully compatible with current chip fabrication technology," says Heinz Schmid, a researcher with IBM's Zurich Research Laboratory and the lead author on the paper, in a statement. "Importantly the method is also economically viable," he adds.
Schmid cautions that more development work will be required to achieve a high-degree of control over the performance of III-V devices created in this way.
A further advantage of the use of III-V compound semiconductors as the active device material rather than silicon is that, it also supports the creation of optoelectronic devices. These could be used to create on-chip light emitters and receivers, which have been touted for the on-chip transmission of high-speed signals.
Len Jenelik, senior director of semiconductor manufacturing at IHS. "The development of a lower cost solution to III-V material structures is a goal that numerous researchers continue to strive for. Adding nanowires for all-around gate control shows improved electrical performance. The challenge remains how to take a lab developed and optimized process and place it in a full manufacturing environment," says Len Jelinek,"The development of nanowire technology has come a long way and eventually a breakthrough technology will be developed to allow for the growth and placement of nanowires."
Jelinek adds that IBM continues to demonstrate leadership and forward-looking technology for the semiconductor industry. This is partly to be expected because IBM has a long history of fundamental semiconductor research and budgeted $3 billion for nanometer-scale R&D over five years in July 2014. However, it is also the case that IBM is paying Globalfoundries Inc. $1.5 billion to take its semiconductor-based business and wafer fabs of its hands.
Questions or comments on this story? Contact peter.clarke@ihs.com
Related links and articles:
IBM's Applied Physics Letters paper
IHS Technology Semiconductors and Components Page
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IBM Pumps $3 Billion Into Nanometer Chip R&D
IBM To Pay Globalfoundries $1.5 Billion to Take Chip Business
