Analog/Mixed Signal

IEDM Spotlights Electron Devices Research Progress for 2016

01 December 2015

Researchers will report on progress in many areas of electronic devices at the International Electron Devices Meeting in Washington, DC next week. The meeting is the bellwether of what the electronics industry can expect in circuit and systems design usually reported in the ISSCC next February and the various conferences throughout 2016.

International Electron Devices Meeting in Washington, DC.International Electron Devices Meeting in Washington, DC.

Here are some of the highlights IEDM participants can expect to hear:

    • Samsung researchers will describe two enabling techniques to wring substantial performance improvements out of state-of-the-art 20nm DRAMs with no need for advanced fabrication techniques like EUV lithography. They developed a honeycomb cell structure that effectively increases cell pitch by 7.5 percent, leading to a 57 percent increase in cell capacitance for improved data retention. They also developed an air-gap spacer arrangement that achieves a 34 percent reduction in bitline capacitance for faster operation.
    • Macronix researchers will describe an alternate 3-D NAND architecture to the gate-all-around (GAA) devices. The researchers created a 2D-like structure consisting of a single-gate, flat-cell thin film transistor with an ultra-thin body that Macronix calls single-gate vertical channel (SGVC). The design can have potentially more than four times the memory density of GAA vertical channels at the same scaling node.
    • Researchers at Taiwan’s National Tsing-Hua University will describe a resistive memory (RRAM) that uses a FinFET transistor for the “select” gate and the FinFET’s HfO2-based resistive dielectric film for a storage node of the RRAM cell. At the 16nm node, the RRAM cell size occupies a mere area of 0.07632μm2 and exhibits low-voltage operation, good retention and excellent reliability overall, according to the researchers.
    • A research team at the National University of Singapore will describe the first use of vertically stacked III-V nanowires to integrate high electron-mobility III-V semiconductors monolithically and cost-effectively with traditional CMOS silicon technology at sub-7 nm technology nodes. The researchers built a sub-150nm high-quality GaSb buffer layer on silicon and multi-gate InAs nFETs and GaSb pFETs from stacked InAs or GaSb nanowires, respectively. The fabrication technology is suitable for both high-performance and low-power logic applications, according to the researchers.
    • National Nano Device Laboratories in Taiwan will describe gate-all-around (GAA) nanowire MOSFETs with diamond-shaped Ge and GeSi nanowire channels. The researchers are seeking to find a way to more effectively use germanium (Ge) as the channel material in multi-gate device configurations for scaling beyond the 10-nm technology node. The researchers sculpted Ge and GeSi nanowires into diamond cross-sectional shapes and used the nanowires as suspended channels in a GAA MOSFET configuration.
    • A team from Japan’s Semiconductor Energy Laboratory Co. will describe how they made 20nm gate-all-around MOSFETs with incredibly low off-state currents of <0.1pA and cutoff frequencies exceeding 10GHz. The transistors were made from thin films of indium-gallium-zinc-oxide (IGZO) and built using a self-aligned process that eliminated overlaps from the gate to the source and drain. Their extremely low off-current allowed for data retention of >10 days at 125°C, when integrated in a DRAM memory cell.
    • Taiwan’s National Nano Device Laboratories researchers used a CO2 far-infrared laser at 400°C to selectively pulse-anneal the source-drain regions areas of the silicon to build a sub-40nm monolithic IC containing a variety of heterogeneous functions—logic, SRAM, RRAM, sense and analog amplifiers, and gas sensors. Low-power, low-cost, small-footprint and heterogeneously integrated devices are possible for the Internet of Things applications, according to the researchers.
    • Fujitsu researchers used InAlGaN and a novel double-layer SiN passivation technique to build 80nm-channel-length InAlGaN/GaN power HEMTs with a record 3 W/mm output power density at 96 GHz, which is a 60 percent improvement over the best results reported to date. The HEMTs’ power and reliability performance is suitable for use in W-band amplifiers (75–110 GHz).
    • A research team from several European research organizations and universities, led by Germany’s Forschungszentrum Jülich institute, will report on a silicon-based direct-bandgap germanium-tin (GeSn) micro-disk laser that emits at a lasing wavelength of 2.5 μm at a power output of 221 kW/cm2. The device was built using standard CMOS-compatible processing and was monolithically integrated on a silicon platform.
    • A team led by Institut d’Electronique de Microélectronique et de Nanotechnologie, has developed what they call an ultimate thinning and transfer-bonding (UTTB) process which they used to build radio-frequency CMOS circuits on a variety of flexible substrates including polyimide plastic film, glass, and stainless steel. According to the researchers the UTTB technique can be adapted to meet application-specific requirements for ultra-mechanical flexibility, heat dissipation and transparency.
    • Researchers at Olympus are using 3D wafer-stacking technology to integrate two separate CMOS imagers into one device, each optimized for either red-green-blue (RGB) visible light, or near-infrared (NIR) wavelengths, through a careful balance of active silicon thickness and pixel size. The top imager is optimized for visible detection with an array of small pixels and a thinned 3µm active silicon layer. NIR signals pass through it to reach the bottom imager, which is optimized for NIR detection with an array of larger pixels and thick active silicon. The researchers say there is no degradation in color reproduction, sensitivity or resolution.
    • IBM researchers have developed what they claim is the largest neuromorphic “core” ever built, a 256 x 256 array of artificial synapses with on-chip programming circuitry. The synapses are 64k-cell phase-change memory (PCM) devices, with each PCM synapse capable of running in one of three modes independently, each of which is an analog of the behavior of real neurons. The three modes includes the so-called leaky-integration-and-fire where the synapse fires when input voltage reaches a certain threshold; the spike-timing dependent plasticity which is an algorithm that mimics a fundamental brain mechanism for learning and memory; and an idle mode.
    • MIT researchers have used nanoscale cold cathodes built from arrays of nanowire field emitters, arrays as large as 1,000 x 1,000, that can be integrated with silicon technology to enable compact RF amplifiers and sources of terahertz, infrared and X-ray energy. They demonstrated a current density of >100 A/cm2, more than a hundredfold greater than any other field-emission cathode operated in continuous wave mode. Each emitter (6-8nm tip diameter) sits atop a vertical silicon nanowire (10µm tall, 100-200nm in diameter). The nanowire acts as a current limiter to protect the emitter from possible damage from heating and arcing.
    • A research team led by Imec will detail an implantable neural probe that has the highest reported density of optrodes (light emitters) and electrodes (to record the responses of the neurons once they are stimulated). High integration was the key. To build the probe, the researchers integrated two different CMOS processes (silicon nitride photonics and TiN electrodes). They built probes 100µm wide and 30µm thick, containing 12 optrodes (6 x 20 µm2 in size) and 24 electrodes (10 x 10 µm2). They packaged the circuitry, implanted it in a mouse brain and successfully demonstrated that it could both drive and record neural activity.

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