Semiconductor Value Chain

Kandou Preps IP to Move Chip Data Faster

06 November 2014

Kandou Bus SA (Lausanne, Switzerland) – an interface technology company specializing in chip-to-chip data transmission that has developed specialized encoding technology – has announced it is developing the Glasswing family of SERDES chip interconnects. The company has started work on a physical layer circuit (PHY) in 28nm CMOS for in-package processor-to-processor links. The circuit is expected to be available for evaluation in the third quarter of 2015.

The company was founded in 2011 by Amin Shokrollahi, a professor of mathematics and computer science at the Swiss Federal Institute, Lausanne (EPFL) and is based on encoding multiple bits on multiple wires in a correlated manner to achieve higher data throughput and lower energy per bit transmitted than can be achieved by conventional methods.

The company calls its technology Chordal signalling and claims it can increase bandwidth by a factor of between 2 and 4 and reduce power consumption by 50 percent compared with conventional data transmission. Kandou points out that differential signalling is, in essence, a simplified version of the general chordal approach limited to two states transmitted over two wires.

Prior to founding Kandou Bus, Professor Shokrollahi served as chief scientist of Digital Fountain Inc. where he invented Raptor codes, which are now used to complement forward error correction in the transmission and reception of digital data streams. 3GPP, DVB, IPTV, and other standards bodies have all standardized on Raptor codes. Qualcomm acquired Digital Foundation in 2009.

Since then, Professor Shokrollahi has worked on the realization of power saving benefits in chip-to-chip interconnect through the use of encoding. Kandou has developed proprietary circuits and architectures for all parts of the transmission chain including drivers, receivers, equalizers, clock and data recovery units, skew detection/mitigation, and support for legacy modes. Chord signalling can be applied to numerous IC applications, Kandou claims, from through-silicon vias (TSVs) for stacked memory die, to interposers for server and switch backplanes.

Glasswing chordal coding shown conceptually. Source: Kandou Bus.

The Glasswing implementation is a chordal code that delivers five bits of data over six correlated wires within each clock cycle and includes a comparator network that yields the bit pattern at the receiver, Kandou said in a statement.

Depending on the application a link can run at up to 25Gbaud (symbols per second) and deliver up to 20.8 Gbits per second per wire at less than 0.5pJ per bit in a 28nm logic process the company said. Kandou argues that these low figures are especially beneficial for links of less than 10mm in length, such as the connection between a DRAM stack and controller, the link to an outbound SERDES, or the on-chip coherency buses of multicore processors. The link can also work over links of up to 25mm in length at higher energy per bit transfer per wire.

While DDR schemes (double data rate) can deliver 16 bits per clock over nine wires, where the ninth wire is used for checksum error correction, they consume multiple picojoules per bit transfer, Jeff McGuire, vice president of business development told Electronics 360, in email correspondence. "Glasswing provides a lot of flexibility to component architects to make trade-offs between bandwidth, power and cost to optimize their multi-chip packaged solutions," he added.

In February 2014 Professor Shokrollahi, presented a paper at the International Solid-State Circuits Conference entitled 'A Pin and Power Efficient Low Latency 8-12Gb/s/wire 8b8w-coded SerDes Link for High Loss Channels in 40nm Technology.'

"Architectures that combine multiple chips into a single package are not new," said Shokrollahi, in a statement, "but increasing bandwidth and improving signal integrity while maintaining very low power in an affordable package is a daunting task. Glasswing delivers on the promise of 2.5D integration by providing a cost-effective solution that offers unprecedented, in-package, chip-to-chip bandwidth at very low power."

Glasswing is one of four different IP product families under development at Kandou Bus. The others are: Wasp being developed for high-speed networks and long-reach cables; Firefly as an augmentation to LPDDR, DDR and GDDR memory links; and Morpho for TSVs and on-chip links.

Related links and articles:

IHS semiconductor value chain research

News articles:

Startup Claims Wireless Communications Breakthrough

Cisco Backs Smart-Grid Modem Startup

Applied Micro Rolls 64-bit Embedded ARM-based CPUs

Powered by CR4, the Engineering Community

Discussion – 0 comments

By posting a comment you confirm that you have read and accept our Posting Rules and Terms of Use.
Engineering Newsletter Signup
Get the Engineering360
Stay up to date on:
Features the top stories, latest news, charts, insights and more on the end-to-end electronics value chain.
Weekly Newsletter
Get news, research, and analysis
on the Electronics industry in your
inbox every week - for FREE
Sign up for our FREE eNewsletter
Find Free Electronics Datasheets