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Memory and Storage

JEDEC Releases Revolutionary LPDDR4 Standard

27 August 2014

Although a couple of chip companies jumped the gun with product introductions global chip standards group the JEDEC Solid State Technology Association (Arlington, Virginia) has published a standard for LPDDR4 for low power memory devices. The standard is intended to double memory throughput and boost efficiency for smartphones, tablet computers and thin notebook computers.

Devices equipped with the LPDDR4 interface will eventually be able to operate at an I/O rate of 4266 million transfers per second, twice that of LPDDR3. LPDDR4 will come in with I/O data rate of 3,200-MT/s compared to 2,133-MT/s for LPDDR3. The architecture of LPDDR4 includes a broadening of the datapath from one channel of 16bits to two channels of 16bits allowing 32bit transfers.

The two-channel architecture also allows the clock and address bus to be grouped together with the data bus. Thus, the skew between data bus to the clock and address bus is minimized, allowing the LPDDR4 device to reach a higher data rate. This saves power and improves timing margins compared to the LPDDR3 architecture.

The JEDEC committee recognized that extending LPDDR3 to high frequencies would consume too much power and has therefore implemented a change in the I/O signalling to a low-voltage swing-terminated logic (LVSTL) range of 367mV or 440mV is less than half that of the voltage swing of LPDDR3. In addition, by using Vssq termination and data bus inversion (DBI), termination power can be minimized since any I/O signal driving a “0” consumes no termination power.

The operating voltage was reduced from 1.2V of previous memory interface generations to 1.1V. In addition, the I/O can operate in an unterminated mode at low frequencies with a reduced voltage swing, and the standard allows rapid switching between operating points so the lower frequency operation can be used whenever possible.

The rapid switching between frequencies is enabled by frequency set point (FSP) registers. LPDDR4 specifies two FSPs, which are copies of all the DRAM registers that store operating parameters which might need to be changed for operation at two different frequencies. Once both operating frequencies are trained, and the parameters stored in each of the two corresponding FSPs, switching between the frequencies can be accomplished by a single mode register write. This reduces the latency for frequency changes, and enables the system to operate at the optimal speed for the workload more often. As with previous low-power DRAM generations, LPDDR4 does not require a delay-locked loop (DLL) or phase-locked loop (PLL).

"LPDDR3 was an evolutionary change from LPDDR2. With LPDDR4, the architecture is completely different," said Hung Vuong, chairman of JC-42.6 sub-committee that worked on the standard. "We knew the only way to achieve the performance that the industry required was to make a total departure from previous generations."

Mian Quddus, chairman of the JEDEC board of directors, commented: "LPDDR4 represents a dramatic performance increase. It is intended to meet the power, bandwidth, packaging, cost and compatibility requirements of the world’s most advanced mobile systems."

To facilitate understanding and adoption of the LPDDR4 standard, JEDEC is hosting an LPDDR4 Workshop in Santa Clara, CA on September 23, 2014. See

The JESD209-4 LPDDR4 standard can be downloaded here.

Related links and articles:

IHS memory research services

News articles:

Samsung, SK Hynix Both Claim First LPDDR4 DRAM

Micron Makes 8Gbit DDR3 DRAM

Samsung Starts Making DRAM at 20nm

Samsung, Rambus Agree $320 million IP Deal

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