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Taiwan's Andes Adds Peripherals IP for IoT, Wearables

04 September 2014

Andes Technology Corp. (Hsinchu, Taiwan), a licensor of 32-bit processor cores, has shifted gears to address the peripherals and peripheral fabric that is also key to producing low-power systems.

The AndeShape AE210P is a configurable platform of peripheral IP cores based on AHB and APB on-chip buses that is intended to provide a low-power subsystem for Internet of Things and wearable device markets.

The platform – effectively a configurable microcontroller template for power-sensitive applications – can be integrated with Andes processor cores, or those from other IP licensors, Andes said. The company is therefore opening up the possibility of integrating cores with is processor IP rivals ARM Holdings plc (Cambridge, England) or Imagination Technologies Group plc (Kings Langley, England).

Typical applications include: smart sensor devices, medical devices, intelligent appliances, touch panels, wireless charging and power management ICs, Andes indicated in a statement.

Andes, founded in 2005, has been seeking to gain design wins for its processor IP with those companies who chose not to afford to license ARM or MIPS cores. It's IP includes a series of 32-bit processor implementations labelled N7, N8, N9, N10 and N13.

The AE210P provides options to select and customers the options to select and tune peripheral IPs the fabric that connects them. A simplified bus structure of a single APB to support basic peripheral IPs requires a gate count of 11,000. Alternatively an AHB bus matrix plus the AHB can provide higher throughput and performance.

In terms of peripheral IPs, the AE210P offers from DMA controller, PWM, watchdog timer, Real Time Clock (RTC), UART controller, SPI controller, I2C Controller and bus controllers for AHB master/slave and APB. Using the standard TSMC 90nm LP library, the AE210P can deliver frequencies up to 200MHz for high-performance applications, while power consumption can be as little as 98-microwatts (82-microamps at 1.2V) for low power mode.

Alternative configurations of the AE210P peripherals platform. Source: Andes Technology.

"The AE210P also enables customers to meet efficiency requirements and speed up their development process," said Charlie Su, CTO at Andes, in a statement. "These benefits are easily demonstrated by its access acceleration for NOR Flash, a typical memory among various MCU applications. It not only offers Serial Peripheral Interface (SPI) for direct program execution from Serial Flash, but also employs the FlashFetch™ technology to accelerate the access time from Parallel Flash."

The combination of the AE210P platform with Andes cores is supported by the AndeSight integrated development environment and board support package. Andes has also worked to demonstrate real-time operating system support with FreeRTOS, ThreadX, and uc/OS-II.

"Our ThreadX RTOS is an ideal match for the power-conscious AE210P, with our small memory footprint and highly efficient code," said William Lamie, president of Express Logic Inc., in the same statement. "ThreadX supports IoT development for wearable and portable devices based on the AE210P, that require efficient, high-performance, and easy-to-use operation."

Related links and articles:

www.andestech.com

IHS MCUs and MPUs research

News articles:

Multi-threading Core Pitched to Beat ARM in Mobile

Imagination Inserts MIPS into Ensigma Radio for IoT

ARM to Open Cortex-M CPU Design Center in Taiwan

Indian Startup Tips Wearable Processor Family



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